================
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple
dxil-pc-shadermodel6.6-library %s \
+// RUN: -emit-llvm -disable-llvm-passes -fnative-int16-type
-fnative-half-type -o - | \
+// RUN: FileCheck %s -check-prefix=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple
spirv-pc-vulkan-library %s \
+// RUN: -emit-llvm -disable-llvm-passes -fnative-int16-type
-fnative-half-type -o - | \
+// RUN: FileCheck %s -check-prefix=CHECK,CHECK-SPV
+
+// CHECK: define {{.*}} <4 x i16> @_Z10test_u8u16u15uint8_t4_packed
+// CHECK-DXIL: [[VAR:%.*]] = call { i16, i16, i16, i16 }
@llvm.dx.unpack.u8u16(i32 %{{.*}})
+// CHECK-DXIL: %{{.*}} = extractvalue { i16, i16, i16, i16 } [[VAR]], 0
+// CHECK-DXIL: %{{.*}} = insertelement <4 x i16>
+// CHECK-DXIL: %{{.*}} = extractvalue { i16, i16, i16, i16 } [[VAR]], 1
+// CHECK-DXIL: %{{.*}} = insertelement <4 x i16>
+// CHECK-DXIL: %{{.*}} = extractvalue { i16, i16, i16, i16 } [[VAR]], 2
+// CHECK-DXIL: %{{.*}} = insertelement <4 x i16>
+// CHECK-DXIL: %{{.*}} = extractvalue { i16, i16, i16, i16 } [[VAR]], 3
+// CHECK-DXIL: %{{.*}} = insertelement <4 x i16>
+// CHECK-DXIL: ret <4 x i16>
----------------
joaosaffran wrote:
The DXIL checks only match `%{{.*}}`, so they don't verify dataflow. Can we
capture the values and check that each element is inserted into the right lane
and that the final vector is returned?
https://github.com/llvm/llvm-project/pull/228518
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