https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/229252
>From cbbe52105702568d2a4f5f61e818f0f40dfcd1f0 Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Mon, 5 Oct 2026 13:37:23 -0700 Subject: [PATCH] [clang][CIR] Add tests for SVE RECPE intrinsics --- .../AArch64/sve-intrinsics/acle_sve_recpe.c | 68 ------------------ clang/test/CodeGen/AArch64/sve/recpe.c | 71 +++++++++++++++++++ 2 files changed, 71 insertions(+), 68 deletions(-) delete mode 100644 clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpe.c create mode 100644 clang/test/CodeGen/AArch64/sve/recpe.c diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpe.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpe.c deleted file mode 100644 index 067512d27d57f..0000000000000 --- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpe.c +++ /dev/null @@ -1,68 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s - -#include <arm_sve.h> - -#if defined __ARM_FEATURE_SME -#define MODE_ATTR __arm_streaming -#else -#define MODE_ATTR -#endif - -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 -#endif - -// CHECK-LABEL: @test_svrecpe_f16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> [[OP:%.*]]) -// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z16test_svrecpe_f16u13__SVFloat16_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] -// -svfloat16_t test_svrecpe_f16(svfloat16_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svrecpe,_f16,,)(op); -} - -// CHECK-LABEL: @test_svrecpe_f32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> [[OP:%.*]]) -// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z16test_svrecpe_f32u13__SVFloat32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] -// -svfloat32_t test_svrecpe_f32(svfloat32_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svrecpe,_f32,,)(op); -} - -// CHECK-LABEL: @test_svrecpe_f64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> [[OP:%.*]]) -// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z16test_svrecpe_f64u13__SVFloat64_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] -// -svfloat64_t test_svrecpe_f64(svfloat64_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svrecpe,_f64,,)(op); -} diff --git a/clang/test/CodeGen/AArch64/sve/recpe.c b/clang/test/CodeGen/AArch64/sve/recpe.c new file mode 100644 index 0000000000000..a25fe89d36bf6 --- /dev/null +++ b/clang/test/CodeGen/AArch64/sve/recpe.c @@ -0,0 +1,71 @@ +// REQUIRES: aarch64-registered-target + +// DEFINE: %{optimize} = opt -passes=mem2reg,tailcallelim -S + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %} + +// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM + +//============================================================================= +// NOTES +// +// Tests for SVE RECPE intrinsics +//============================================================================= + +#include <arm_sve.h> + +#if defined __ARM_FEATURE_SME +#define MODE_ATTR __arm_streaming +#else +#define MODE_ATTR +#endif + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// C-LABEL: @test_svrecpe_f16( +// CPP-LABEL: @_Z16test_svrecpe_f16u13__SVFloat16_t( +svfloat16_t test_svrecpe_f16(svfloat16_t op) MODE_ATTR +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.frecpe.x" %{{.*}} : (!cir.vector<[8] x !cir.f16>) -> !cir.vector<[8] x !cir.f16> + +// LLVM-SAME: <vscale x 8 x half> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> [[OP]]) +// LLVM: ret <vscale x 8 x half> [[TMP0]] + return SVE_ACLE_FUNC(svrecpe,_f16,,)(op); +} + +// C-LABEL: @test_svrecpe_f32( +// CPP-LABEL: @_Z16test_svrecpe_f32u13__SVFloat32_t( +svfloat32_t test_svrecpe_f32(svfloat32_t op) MODE_ATTR +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.frecpe.x" %{{.*}} : (!cir.vector<[4] x !cir.float>) -> !cir.vector<[4] x !cir.float> + +// LLVM-SAME: <vscale x 4 x float> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> [[OP]]) +// LLVM: ret <vscale x 4 x float> [[TMP0]] + return SVE_ACLE_FUNC(svrecpe,_f32,,)(op); +} + +// C-LABEL: @test_svrecpe_f64( +// CPP-LABEL: @_Z16test_svrecpe_f64u13__SVFloat64_t( +svfloat64_t test_svrecpe_f64(svfloat64_t op) MODE_ATTR +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.frecpe.x" %{{.*}} : (!cir.vector<[2] x !cir.double>) -> !cir.vector<[2] x !cir.double> + +// LLVM-SAME: <vscale x 2 x double> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> [[OP]]) +// LLVM: ret <vscale x 2 x double> [[TMP0]] + return SVE_ACLE_FUNC(svrecpe,_f64,,)(op); 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