================
@@ -506,6 +507,35 @@ void AArch64AsmPrinter::emitFunctionHeaderComment() {
OutStreamer->getCommentOS() << ' ' << OutlinerString;
}
+void AArch64AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI) {
+ assert(MI.getOperand(0).getImm() == 4 &&
+ "Expected a single patchable AArch64 instruction");
+
+ const MachineBasicBlock &MBB = *MI.getParent();
+ const auto *TII = STI->getInstrInfo();
+ auto NextMI =
+ std::find_if(std::next(MI.getIterator()), MBB.end().getInstrIterator(),
+ [&](const MachineInstr &Next) {
+ return Next.isInlineAsm() ||
+ (!AArch64InstrInfo::isSEHInstruction(Next) &&
+ TII->getInstSizeInBytes(Next) != 0);
+ });
+
+ // Every AArch64 instruction is atomically patchable. If this block emits no
+ // instructions, however, the next block would share the function's entry
+ // address. Pad it so a backedge cannot reach the hotpatch instruction. As on
+ // x86, conservatively pad inline assembly, whose first instruction may have
+ // a label targeted by branches within the assembly.
+ if (NextMI == MBB.end() || NextMI->isInlineAsm()) {
+ emitNops(1);
+ if (MF->hasWinCFI()) {
+ auto *TS = static_cast<AArch64TargetStreamer *>(
+ OutStreamer->getTargetStreamer());
+ TS->emitARM64WinCFINop();
----------------
efriedma-quic wrote:
How hard would it be to emit the nop after the seh_endprologue? That avoids
emitting unnecessary unwind info.
https://github.com/llvm/llvm-project/pull/229477
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