llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Changpeng Fang (changpeng) <details> <summary>Changes</summary> The D# tensor descriptor groups of __builtin_amdgcn_tensor_load_to_lds and __builtin_amdgcn_tensor_store_from_lds are bit fields, not signed values. D0 was already declared as a vector of unsigned int; D1 through D4 are now consistent with it. OpenCL does not allow lax vector conversions, so the tests are updated to pass unsigned vectors. The generated IR is unchanged. Reference: https://github.com/llvm/llvm-project/pull/193310 --- Full diff: https://github.com/llvm/llvm-project/pull/230714.diff 3 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsAMDGPU.td (+2-2) - (modified) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl (+13-15) - (modified) clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl (+2-2) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.td b/clang/include/clang/Basic/BuiltinsAMDGPU.td index 483df0561fc20e..33b12b64baaec0 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.td +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.td @@ -1039,11 +1039,11 @@ def __builtin_amdgcn_global_store_async_from_lds_b128 : AMDGPUBuiltin<"void(_Ext def __builtin_amdgcn_ds_atomic_async_barrier_arrive_b64 : AMDGPUBuiltin<"void(long int address_space<3> *)", [Const], "gfx1250-insts">; def __builtin_amdgcn_ds_atomic_barrier_arrive_rtn_b64 : AMDGPUBuiltin<"long int(long int address_space<3> *, long int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_tensor_load_to_lds : AMDGPUBuiltin<"void(_ExtVector<4, unsigned int>, _ExtVector<8, int>, _ExtVector<4, int>, _ExtVector<4, int>, _ExtVector<8, int>, _Constant int)", [Const], "tdm-insts"> { +def __builtin_amdgcn_tensor_load_to_lds : AMDGPUBuiltin<"void(_ExtVector<4, unsigned int>, _ExtVector<8, unsigned int>, _ExtVector<4, unsigned int>, _ExtVector<4, unsigned int>, _ExtVector<8, unsigned int>, _Constant int)", [Const], "tdm-insts"> { let Documentation = [DocTensorLoadToLDS_GFX1250]; let ArgNames = ["D0", "D1", "D2", "D3", "D4", "cpol"]; } -def __builtin_amdgcn_tensor_store_from_lds : AMDGPUBuiltin<"void(_ExtVector<4, unsigned int>, _ExtVector<8, int>, _ExtVector<4, int>, _ExtVector<4, int>, _ExtVector<8, int>, _Constant int)", [Const], "tdm-insts"> { +def __builtin_amdgcn_tensor_store_from_lds : AMDGPUBuiltin<"void(_ExtVector<4, unsigned int>, _ExtVector<8, unsigned int>, _ExtVector<4, unsigned int>, _ExtVector<4, unsigned int>, _ExtVector<8, unsigned int>, _Constant int)", [Const], "tdm-insts"> { let Documentation = [DocTensorStoreFromLDS_GFX1250]; let ArgNames = ["D0", "D1", "D2", "D3", "D4", "cpol"]; } diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl index 23fa72e3532972..53509f8730c20b 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl @@ -2,22 +2,20 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgpu12.50-unknown-unknown -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-GFX1250 -typedef int v4i __attribute__((ext_vector_type(4))); -typedef int v8i __attribute__((ext_vector_type(8))); - typedef unsigned int v4u __attribute__((ext_vector_type(4))); +typedef unsigned int v8u __attribute__((ext_vector_type(8))); -static v4i v4i_zeros = (v4i){0,0,0,0}; -static v8i v8i_zeros = (v8i){0,0,0,0,0,0,0,0}; +static v4u v4u_zeros = (v4u){0,0,0,0}; +static v8u v8u_zeros = (v8u){0,0,0,0,0,0,0,0}; // CHECK-GFX1250-LABEL: @test_amdgcn_tensor_load_to_lds_d4( // CHECK-GFX1250-NEXT: entry: // CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> zeroinitializer, i32 0) // CHECK-GFX1250-NEXT: ret void // -void test_amdgcn_tensor_load_to_lds_d4(v4u sg0, v8i sg1, v4i sg2, v4i sg3) +void test_amdgcn_tensor_load_to_lds_d4(v4u sg0, v8u sg1, v4u sg2, v4u sg3) { - __builtin_amdgcn_tensor_load_to_lds(sg0, sg1, sg2, sg3, v8i_zeros, 0); + __builtin_amdgcn_tensor_load_to_lds(sg0, sg1, sg2, sg3, v8u_zeros, 0); } // CHECK-GFX1250-LABEL: @test_amdgcn_tensor_load_to_lds_d2( @@ -25,9 +23,9 @@ void test_amdgcn_tensor_load_to_lds_d4(v4u sg0, v8i sg1, v4i sg2, v4i sg3) // CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 27) // CHECK-GFX1250-NEXT: ret void // -void test_amdgcn_tensor_load_to_lds_d2(v4u sg0, v8i sg1) +void test_amdgcn_tensor_load_to_lds_d2(v4u sg0, v8u sg1) { - __builtin_amdgcn_tensor_load_to_lds(sg0, sg1, v4i_zeros, v4i_zeros, v8i_zeros, 27); + __builtin_amdgcn_tensor_load_to_lds(sg0, sg1, v4u_zeros, v4u_zeros, v8u_zeros, 27); } // CHECK-GFX1250-LABEL: @test_amdgcn_tensor_store_from_lds_d4( @@ -35,9 +33,9 @@ void test_amdgcn_tensor_load_to_lds_d2(v4u sg0, v8i sg1) // CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> zeroinitializer, i32 22) // CHECK-GFX1250-NEXT: ret void // -void test_amdgcn_tensor_store_from_lds_d4(v4u sg0, v8i sg1, v4i sg2, v4i sg3) +void test_amdgcn_tensor_store_from_lds_d4(v4u sg0, v8u sg1, v4u sg2, v4u sg3) { - __builtin_amdgcn_tensor_store_from_lds(sg0, sg1, sg2, sg3, v8i_zeros, 22); + __builtin_amdgcn_tensor_store_from_lds(sg0, sg1, sg2, sg3, v8u_zeros, 22); } // CHECK-GFX1250-LABEL: @test_amdgcn_tensor_store_from_lds_d2( @@ -45,9 +43,9 @@ void test_amdgcn_tensor_store_from_lds_d4(v4u sg0, v8i sg1, v4i sg2, v4i sg3) // CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0) // CHECK-GFX1250-NEXT: ret void // -void test_amdgcn_tensor_store_from_lds_d2(v4u sg0, v8i sg1) +void test_amdgcn_tensor_store_from_lds_d2(v4u sg0, v8u sg1) { - __builtin_amdgcn_tensor_store_from_lds(sg0, sg1, v4i_zeros, v4i_zeros, v8i_zeros, 0); + __builtin_amdgcn_tensor_store_from_lds(sg0, sg1, v4u_zeros, v4u_zeros, v8u_zeros, 0); } //======================================================================= @@ -62,7 +60,7 @@ void test_amdgcn_tensor_store_from_lds_d2(v4u sg0, v8i sg1) // CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> [[SG4:%.*]], i32 0) // CHECK-GFX1250-NEXT: ret void // -void test_amdgcn_tensor_load_to_lds_d5(v4u sg0, v8i sg1, v4i sg2, v4i sg3, v8i sg4) +void test_amdgcn_tensor_load_to_lds_d5(v4u sg0, v8u sg1, v4u sg2, v4u sg3, v8u sg4) { __builtin_amdgcn_tensor_load_to_lds(sg0, sg1, sg2, sg3, sg4, 0); } @@ -72,7 +70,7 @@ void test_amdgcn_tensor_load_to_lds_d5(v4u sg0, v8i sg1, v4i sg2, v4i sg3, v8i s // CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> [[SG4:%.*]], i32 0) // CHECK-GFX1250-NEXT: ret void // -void test_amdgcn_tensor_store_from_lds_d5(v4u sg0, v8i sg1, v4i sg2, v4i sg3, v8i sg4) +void test_amdgcn_tensor_store_from_lds_d5(v4u sg0, v8u sg1, v4u sg2, v4u sg3, v8u sg4) { __builtin_amdgcn_tensor_store_from_lds(sg0, sg1, sg2, sg3, sg4, 0); } diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl index 8c60b567ddc21c..0fdf8df507bec7 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl @@ -19,9 +19,9 @@ typedef short __attribute__((ext_vector_type(2))) short2; typedef unsigned short __attribute__((ext_vector_type(2))) ushort2; typedef int v4i __attribute__((ext_vector_type(4))); -typedef int v8i __attribute__((ext_vector_type(8))); typedef unsigned int v4u __attribute__((ext_vector_type(4))); +typedef unsigned int v8u __attribute__((ext_vector_type(8))); void test_setprio_inc_wg(short a) { __builtin_amdgcn_s_setprio_inc_wg(a); // expected-error {{'__builtin_amdgcn_s_setprio_inc_wg' must be a constant integer}} @@ -185,7 +185,7 @@ void test_amdgcn_async_load_store_lds_cpol(global char* gaddr8, global int *gadd __builtin_amdgcn_global_store_async_from_lds_b128(gaddr128, laddr128, 16, cpol); // expected-error {{'__builtin_amdgcn_global_store_async_from_lds_b128' must be a constant integer}} } -void test_amdgcn_tensor_load_store(v4u sg0, v8i sg1, v4i sg2, v4i sg3, v8i sg4, int cpol) +void test_amdgcn_tensor_load_store(v4u sg0, v8u sg1, v4u sg2, v4u sg3, v8u sg4, int cpol) { __builtin_amdgcn_tensor_load_to_lds(sg0, sg1, sg2, sg3, sg4, cpol); // expected-error {{'__builtin_amdgcn_tensor_load_to_lds' must be a constant integer}} __builtin_amdgcn_tensor_store_from_lds(sg0, sg1, sg2, sg3, sg4, cpol); // expected-error {{'__builtin_amdgcn_tensor_store_from_lds' must be a constant integer}} `````````` </details> https://github.com/llvm/llvm-project/pull/230714 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
