Author: Craig Topper Date: 2026-10-11T11:42:47-07:00 New Revision: 9dd80b72fa9bda73f1b31ed4e93faac86de687c6
URL: https://github.com/llvm/llvm-project/commit/9dd80b72fa9bda73f1b31ed4e93faac86de687c6 DIFF: https://github.com/llvm/llvm-project/commit/9dd80b72fa9bda73f1b31ed4e93faac86de687c6.diff LOG: [RISCV][P-ext] Re-generate rvp-intrinsics.c. NFC (#230691) This fixes cases that used RV32 and RV64 instead of the common CHECK. This also fixes cases where a mix of CHECK and RV32/RV64 were used in the same function. The script is unable to do this so they must have been manually written. Manual checks place burden on future editors of this file since they can't use the script output directly. Added: Modified: clang/test/CodeGen/RISCV/rvp-intrinsics.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 41f94d48d8de2..375502f2211db 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -5512,79 +5512,121 @@ int32x2_t test_pwsla_s_i32x2(int16x2_t rs1, unsigned shamt) { return __riscv_pwsla_s_i32x2(rs1, shamt); } -// CHECK-LABEL: define dso_local i32 @test_pnsrl_s_u8x4( +// RV32-LABEL: define dso_local i32 @test_pnsrl_s_u8x4( // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsrl.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnsrl_s_u8x4( // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsrl.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 -// CHECK-NEXT: ret i32 [[TMP2]] +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsrl.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] // uint8x4_t test_pnsrl_s_u8x4(uint16x4_t rs1, unsigned shamt) { return __riscv_pnsrl_s_u8x4(rs1, shamt); } -// CHECK-LABEL: define dso_local i32 @test_pnsrl_s_u16x2( +// RV32-LABEL: define dso_local i32 @test_pnsrl_s_u16x2( // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsrl.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnsrl_s_u16x2( // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsrl.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 -// CHECK-NEXT: ret i32 [[TMP2]] +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsrl.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] // uint16x2_t test_pnsrl_s_u16x2(uint32x2_t rs1, unsigned shamt) { return __riscv_pnsrl_s_u16x2(rs1, shamt); } -// CHECK-LABEL: define dso_local i32 @test_pnsra_s_i8x4( +// RV32-LABEL: define dso_local i32 @test_pnsra_s_i8x4( // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsra.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnsra_s_i8x4( // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsra.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 -// CHECK-NEXT: ret i32 [[TMP2]] +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsra.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] // int8x4_t test_pnsra_s_i8x4(int16x4_t rs1, unsigned shamt) { return __riscv_pnsra_s_i8x4(rs1, shamt); } -// CHECK-LABEL: define dso_local i32 @test_pnsra_s_i16x2( +// RV32-LABEL: define dso_local i32 @test_pnsra_s_i16x2( // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsra.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnsra_s_i16x2( // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsra.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 -// CHECK-NEXT: ret i32 [[TMP2]] +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsra.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] // int16x2_t test_pnsra_s_i16x2(int32x2_t rs1, unsigned shamt) { return __riscv_pnsra_s_i16x2(rs1, shamt); } -// CHECK-LABEL: define dso_local i32 @test_pnsrar_s_i8x4( +// RV32-LABEL: define dso_local i32 @test_pnsrar_s_i8x4( // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsrar.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnsrar_s_i8x4( // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsrar.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 -// CHECK-NEXT: ret i32 [[TMP2]] +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.pnsrar.v4i8.v4i16(<4 x i16> [[TMP0]], i32 [[SHAMT]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] // int8x4_t test_pnsrar_s_i8x4(int16x4_t rs1, unsigned shamt) { return __riscv_pnsrar_s_i8x4(rs1, shamt); } -// CHECK-LABEL: define dso_local i32 @test_pnsrar_s_i16x2( +// RV32-LABEL: define dso_local i32 @test_pnsrar_s_i16x2( // RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsrar.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnsrar_s_i16x2( // RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsrar.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 -// CHECK-NEXT: ret i32 [[TMP2]] +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pnsrar.v2i16.v2i32(<2 x i32> [[TMP0]], i32 [[SHAMT]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] // int16x2_t test_pnsrar_s_i16x2(int32x2_t rs1, unsigned shamt) { return __riscv_pnsrar_s_i16x2(rs1, shamt); @@ -9177,177 +9219,105 @@ uint32x2_t test_pwunzipho_u32x2(uint16x4_t a) { /* Packed Slide 1 up/down (32-bit) */ -// RV32-LABEL: define dso_local i32 @test_pslide1up_i8x4( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1up_i8x4( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1up_i8x4( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // int8x4_t test_pslide1up_i8x4(int8x4_t rd, int8_t rs1) { return __riscv_pslide1up_i8x4(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1up_u8x4( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1up_u8x4( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1up_u8x4( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // uint8x4_t test_pslide1up_u8x4(uint8x4_t rd, uint8_t rs1) { return __riscv_pslide1up_u8x4(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1up_i16x2( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 2, i32 0> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1up_i16x2( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 2, i32 0> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1up_i16x2( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 2, i32 0> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // int16x2_t test_pslide1up_i16x2(int16x2_t rd, int16_t rs1) { return __riscv_pslide1up_i16x2(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1up_u16x2( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 2, i32 0> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1up_u16x2( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 2, i32 0> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1up_u16x2( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 2, i32 0> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // uint16x2_t test_pslide1up_u16x2(uint16x2_t rd, uint16_t rs1) { return __riscv_pslide1up_u16x2(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1down_i8x4( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1down_i8x4( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1down_i8x4( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // int8x4_t test_pslide1down_i8x4(int8x4_t rd, int8_t rs1) { return __riscv_pslide1down_i8x4(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1down_u8x4( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1down_u8x4( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1down_u8x4( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // uint8x4_t test_pslide1down_u8x4(uint8x4_t rd, uint8_t rs1) { return __riscv_pslide1down_u8x4(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1down_i16x2( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 1, i32 2> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1down_i16x2( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 1, i32 2> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1down_i16x2( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 1, i32 2> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // int16x2_t test_pslide1down_i16x2(int16x2_t rd, int16_t rs1) { return __riscv_pslide1down_i16x2(rd, rs1); } -// RV32-LABEL: define dso_local i32 @test_pslide1down_u16x2( -// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 1, i32 2> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV32-NEXT: ret i32 [[TMP1]] -// -// RV64-LABEL: define dso_local i32 @test_pslide1down_u16x2( -// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> -// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 1, i32 2> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 -// RV64-NEXT: ret i32 [[TMP1]] +// CHECK-LABEL: define dso_local i32 @test_pslide1down_u16x2( +// CHECK-SAME: i32 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <2 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[VECINIT2_I]], <2 x i32> <i32 1, i32 2> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32 +// CHECK-NEXT: ret i32 [[TMP1]] // uint16x2_t test_pslide1down_u16x2(uint16x2_t rd, uint16_t rs1) { return __riscv_pslide1down_u16x2(rd, rs1); @@ -9355,89 +9325,53 @@ uint16x2_t test_pslide1down_u16x2(uint16x2_t rd, uint16_t rs1) { /* Packed Slide 1 up/down (64-bit) */ -// RV32-LABEL: define dso_local i64 @test_pslide1up_i8x8( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV32-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1up_i8x8( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV64-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1up_i8x8( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> +// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // int8x8_t test_pslide1up_i8x8(int8x8_t rd, int8_t rs1) { return __riscv_pslide1up_i8x8(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1up_u8x8( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV32-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1up_u8x8( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV64-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1up_u8x8( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> +// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // uint8x8_t test_pslide1up_u8x8(uint8x8_t rd, uint8_t rs1) { return __riscv_pslide1up_u8x8(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1up_i16x4( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1up_i16x4( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1up_i16x4( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // int16x4_t test_pslide1up_i16x4(int16x4_t rd, int16_t rs1) { return __riscv_pslide1up_i16x4(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1up_u16x4( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1up_u16x4( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1up_u16x4( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 4, i32 0, i32 1, i32 2> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // uint16x4_t test_pslide1up_u16x4(uint16x4_t rd, uint16_t rs1) { return __riscv_pslide1up_u16x4(rd, rs1); @@ -9487,89 +9421,53 @@ uint32x2_t test_pslide1up_u32x2(uint32x2_t rd, uint32_t rs1) { return __riscv_pslide1up_u32x2(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1down_i8x8( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV32-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1down_i8x8( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV64-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1down_i8x8( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> +// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // int8x8_t test_pslide1down_i8x8(int8x8_t rd, int8_t rs1) { return __riscv_pslide1down_i8x8(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1down_u8x8( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV32-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1down_u8x8( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> -// RV64-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1down_u8x8( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i8 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8> +// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <8 x i8> poison, i8 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[VECINIT8_I]], <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // uint8x8_t test_pslide1down_u8x8(uint8x8_t rd, uint8_t rs1) { return __riscv_pslide1down_u8x8(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1down_i16x4( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1down_i16x4( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1down_i16x4( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef signext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // int16x4_t test_pslide1down_i16x4(int16x4_t rd, int16_t rs1) { return __riscv_pslide1down_i16x4(rd, rs1); } -// RV32-LABEL: define dso_local i64 @test_pslide1down_u16x4( -// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV32-NEXT: [[ENTRY:.*:]] -// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV32-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV32-NEXT: ret i64 [[TMP1]] -// -// RV64-LABEL: define dso_local i64 @test_pslide1down_u16x4( -// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { -// RV64-NEXT: [[ENTRY:.*:]] -// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> -// RV64-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 -// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> -// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 -// RV64-NEXT: ret i64 [[TMP1]] +// CHECK-LABEL: define dso_local i64 @test_pslide1down_u16x4( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i16 noundef zeroext [[RS1:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <4 x i16> poison, i16 [[RS1]], i64 0 +// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[VECINIT4_I]], <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// CHECK-NEXT: ret i64 [[TMP1]] // uint16x4_t test_pslide1down_u16x4(uint16x4_t rd, uint16_t rs1) { return __riscv_pslide1down_u16x4(rd, rs1); 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