================
@@ -48,6 +47,29 @@ static mlir::Value emitAMDGPUDispatchPtr(CIRGenFunction &cgf,
return builder.createAddrSpaceCast(loc, call, expectedPtrTy);
}
+// Load a \p ty value at byte \p offset from \p base as an invariant load.
+static mlir::Value emitAMDGPUInvariantLoad(CIRGenFunction &cgf,
+ mlir::Location loc, mlir::Value
base,
+ mlir::Value offset, mlir::Type ty,
+ CharUnits align) {
+ CIRGenBuilderTy &builder = cgf.getBuilder();
+ mlir::Value addr = builder.createPtrStride(loc, base, offset);
+ cir::LoadOp load = builder.createAlignedLoad(loc, ty, addr, align);
+ load.setInvariant(true);
+ assert(!cir::MissingFeatures::opLoadRangeNoundefMetadata());
+ return load;
+}
+
+static mlir::Value emitAMDGPUGridSize(CIRGenFunction &cgf, mlir::Location loc,
+ unsigned index) {
+ CIRGenBuilderTy &builder = cgf.getBuilder();
+ mlir::Value dispatchPtr = emitAMDGPUDispatchPtr(cgf, loc);
+ // Indexing the HSA kernel_dispatch_packet struct.
+ return emitAMDGPUInvariantLoad(
+ cgf, loc, dispatchPtr, builder.getUInt64(12 + index * 4, loc),
----------------
aobolensk wrote:
Done, thanks
https://github.com/llvm/llvm-project/pull/230798
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