github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h,cl --
clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-schedule-bank.cl
llvm/lib/Target/AMDGPU/AMDGPUScheduleBank.cpp
llvm/lib/Target/AMDGPU/AMDGPUScheduleBank.h
clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp clang/lib/Sema/SemaAMDGPU.cpp
clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250.cl
llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
index c1740763e..0f73b36cc 100644
--- a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
@@ -2295,8 +2295,8 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
// Default: strict (bank | 4)
EncodedBank = Builder.CreateOr(Bank, Builder.getInt32(4));
}
- llvm::Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_schedule_bank,
- Val->getType());
+ llvm::Function *F =
+ CGM.getIntrinsic(Intrinsic::amdgcn_schedule_bank, Val->getType());
return Builder.CreateCall(F, {Val, EncodedBank});
}
default:
diff --git a/clang/lib/Sema/SemaAMDGPU.cpp b/clang/lib/Sema/SemaAMDGPU.cpp
index de54e5739..6a467f39f 100644
--- a/clang/lib/Sema/SemaAMDGPU.cpp
+++ b/clang/lib/Sema/SemaAMDGPU.cpp
@@ -472,10 +472,9 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(const
TargetInfo &TI,
QualType DataTy = DataArg->getType();
if (DataTy->isAnyComplexType() ||
!(DataTy->isArithmeticType() ||
- (DataTy->isVectorType() &&
- DataTy->castAs<VectorType>()
- ->getElementType()
- ->isArithmeticType()))) {
+ (DataTy->isVectorType() && DataTy->castAs<VectorType>()
+ ->getElementType()
+ ->isArithmeticType()))) {
SemaRef.Diag(DataArg->getBeginLoc(),
diag::err_typecheck_cond_expect_int_float)
<< DataTy << DataArg->getSourceRange();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index a8e194958..45d9bad61 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -3363,18 +3363,26 @@ void
AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *N) {
}
unsigned PseudoOpc;
switch (N->getValueType(0).getSizeInBits()) {
- case 32: PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B32; break;
- case 64: PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B64; break;
- case 128: PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B128; break;
- case 256: PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B256; break;
+ case 32:
+ PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B32;
+ break;
+ case 64:
+ PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B64;
+ break;
+ case 128:
+ PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B128;
+ break;
+ case 256:
+ PseudoOpc = AMDGPU::V_SCHEDULE_BANK_B256;
+ break;
default:
// Unsupported width: drop the hint, forward the value unchanged.
ReplaceUses(SDValue(N, 0), Src);
CurDAG->RemoveDeadNode(N);
return;
}
- SDValue BankImm = CurDAG->getTargetConstant(BankC->getZExtValue(),
SDLoc(N),
- MVT::i32);
+ SDValue BankImm =
+ CurDAG->getTargetConstant(BankC->getZExtValue(), SDLoc(N), MVT::i32);
CurDAG->SelectNodeTo(N, PseudoOpc, N->getVTList(), {Src, BankImm});
return;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUScheduleBank.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUScheduleBank.cpp
index fb2cc1651..8427b751b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUScheduleBank.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUScheduleBank.cpp
@@ -7,19 +7,19 @@
//===----------------------------------------------------------------------===//
//
/// \file
-/// Lower the V_SCHEDULE_BANK_B* pseudos produced from
llvm.amdgcn.schedule.bank.
-/// For each pseudo this pass:
+/// Lower the V_SCHEDULE_BANK_B* pseudos produced from
+/// llvm.amdgcn.schedule.bank. For each pseudo this pass:
/// 1. reads the requested bank (0-3) from the immediate operand,
/// 2. attaches an AMDGPURI::BankHint register allocation hint to the
-/// destination (and source) vreg so the allocator prefers that
256-register
-/// bank,
+/// destination (and source) vreg so the allocator prefers that
+/// 256-register bank,
/// 3. propagates the hint through COPY / REG_SEQUENCE / INSERT_SUBREG /
/// SUBREG_TO_REG so it survives coalescing, and
/// 4. replaces the pseudo with a plain COPY.
///
-/// The hint is advisory: SIRegisterInfo::getRegAllocationHints only reorders
the
-/// allocation candidates, so a full bank falls back to the default order and
the
-/// pass never forces a spill.
+/// The hint is advisory: SIRegisterInfo::getRegAllocationHints only reorders
+/// the allocation candidates, so a full bank falls back to the default order
+/// and the pass never forces a spill.
//
//===----------------------------------------------------------------------===//
@@ -118,18 +118,18 @@ static bool runScheduleBank(MachineFunction &MF) {
}
LLVM_DEBUG(dbgs() << " schedule.bank: " << printReg(DstReg) << " <- "
- << printReg(SrcReg) << " bank " << Bank
- << " strict " << Strict << '\n');
+ << printReg(SrcReg) << " bank " << Bank << " strict "
+ << Strict << '\n');
// Hint both the destination and the source so the preference survives
// whichever side coalescing keeps.
if (DstReg.isVirtual() &&
- (Strict || MRI.getRegAllocationHint(DstReg).first !=
- AMDGPURI::StrictBankHint))
+ (Strict ||
+ MRI.getRegAllocationHint(DstReg).first != AMDGPURI::StrictBankHint))
MRI.setRegAllocationHint(DstReg, HintKind, Bank);
if (SrcReg.isVirtual() &&
- (Strict || MRI.getRegAllocationHint(SrcReg).first !=
- AMDGPURI::StrictBankHint))
+ (Strict ||
+ MRI.getRegAllocationHint(SrcReg).first != AMDGPURI::StrictBankHint))
MRI.setRegAllocationHint(SrcReg, HintKind, Bank);
SmallDenseSet<unsigned, 32> Visited;
@@ -173,8 +173,8 @@ public:
} // end anonymous namespace
-INITIALIZE_PASS(AMDGPUScheduleBank, DEBUG_TYPE, "AMDGPU Schedule Bank",
- false, false)
+INITIALIZE_PASS(AMDGPUScheduleBank, DEBUG_TYPE, "AMDGPU Schedule Bank", false,
+ false)
char AMDGPUScheduleBank::ID = 0;
@@ -182,7 +182,7 @@ char &llvm::AMDGPUScheduleBankID = AMDGPUScheduleBank::ID;
PreservedAnalyses
AMDGPUScheduleBankPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
+ MachineFunctionAnalysisManager &MFAM) {
if (!runScheduleBank(MF))
return PreservedAnalyses::all();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index effb29be1..b687c3b80 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -32,10 +32,10 @@
#include "AMDGPUPerfHintAnalysis.h"
#include "AMDGPUPreloadKernArgProlog.h"
#include "AMDGPUPrepareAGPRAlloc.h"
-#include "AMDGPUScheduleBank.h"
#include "AMDGPURemoveIncompatibleFunctions.h"
#include "AMDGPUReserveWWMRegs.h"
#include "AMDGPUResourceUsageAnalysis.h"
+#include "AMDGPUScheduleBank.h"
#include "AMDGPUSplitModule.h"
#include "AMDGPUTargetObjectFile.h"
#include "AMDGPUTargetTransformInfo.h"
``````````
</details>
https://github.com/llvm/llvm-project/pull/227953
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