Author: SiHuaN Date: 2026-10-15T15:56:54Z New Revision: 4be1a8f7fcc172fd7b50a6c2779b7b90240ec1cc
URL: https://github.com/llvm/llvm-project/commit/4be1a8f7fcc172fd7b50a6c2779b7b90240ec1cc DIFF: https://github.com/llvm/llvm-project/commit/4be1a8f7fcc172fd7b50a6c2779b7b90240ec1cc.diff LOG: [Clang][RISCV] Require 64bit for __builtin_riscv_rev16_64 (#232362) Added: clang/test/CodeGen/RISCV/riscv32-p-error.c Modified: clang/include/clang/Basic/BuiltinsRISCV.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 9004c815c8a1e..d496333952052 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -262,7 +262,8 @@ def pmerge_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned def pmerge_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<2, unsigned int>, _Vector<2, unsigned int>)">; // Scalar Bitmanip -def rev16_64 : RISCVBuiltin<"uint64_t(uint64_t)", "64bit">; +let Features = "experimental-p,64bit" in +def rev16_64 : RISCVBuiltin<"uint64_t(uint64_t)">; // Scalar Averaging Addition and Subtraction def aadd_i32 : RISCVBuiltin<"int32_t(int32_t, int32_t)">; diff --git a/clang/test/CodeGen/RISCV/riscv32-p-error.c b/clang/test/CodeGen/RISCV/riscv32-p-error.c new file mode 100644 index 0000000000000..69632be438e4c --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv32-p-error.c @@ -0,0 +1,5 @@ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-p -S -verify %s -o - + +unsigned long long rev16_64(unsigned long long a) { + return __builtin_riscv_rev16_64(a); // expected-error {{'__builtin_riscv_rev16_64' needs target feature experimental-p,64bit}} +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
