llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-spir-v Author: Alex Voicu (AlexVlx) <details> <summary>Changes</summary> Creating constants at the point of observation / use can lead, in complex control-flow, to their referencing by previous instructions, which yields broken MIR. This change uses the dedicated interface to ensure that constants are always created in the entry block and thus dominate all uses. It is mostly NFC asides from tweaking tests that were order dependent. --- Full diff: https://github.com/llvm/llvm-project/pull/234291.diff 5 Files Affected: - (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+15-15) - (modified) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all_memory_barrier_with_group_sync.ll (+1-1) - (modified) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/device_memory_barrier_with_group_sync.ll (+1-1) - (modified) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier.ll (+1-1) - (modified) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll (+1-1) ``````````diff diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index fbbf00dbb6c05d..083ab6db784797 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2146,7 +2146,7 @@ bool SPIRVInstructionSelector::selectAtomicLoad(Register ResVReg, uint32_t Scope = static_cast<uint32_t>( getMemScope(STI.getTargetTriple(), Context, MemOp.getSyncScopeID())); - Register ScopeReg = buildI32Constant(Scope, I); + Register ScopeReg = buildI32ConstantInEntryBlock(Scope, I); AtomicOrdering AO = MemOp.getSuccessOrdering(); uint32_t StorageClass = static_cast<uint32_t>(getMemSemanticsForStorageClass( @@ -2156,7 +2156,7 @@ bool SPIRVInstructionSelector::selectAtomicLoad(Register ResVReg, MemSem |= static_cast<uint32_t>(SPIRV::MemorySemantics::Volatile); uint32_t Sem = getMemSemanticsWithStorageClass(STI.getTargetTriple(), MemSem, StorageClass); - Register MemSemReg = buildI32Constant(Sem, I); + Register MemSemReg = buildI32ConstantInEntryBlock(Sem, I); MachineIRBuilder MIRBuilder(I); @@ -2322,7 +2322,7 @@ bool SPIRVInstructionSelector::selectAtomicStore(MachineInstr &I) const { uint32_t Scope = static_cast<uint32_t>( getMemScope(STI.getTargetTriple(), Context, MemOp.getSyncScopeID())); - Register ScopeReg = buildI32Constant(Scope, I); + Register ScopeReg = buildI32ConstantInEntryBlock(Scope, I); AtomicOrdering AO = MemOp.getSuccessOrdering(); uint32_t StorageClass = static_cast<uint32_t>(getMemSemanticsForStorageClass( @@ -2332,7 +2332,7 @@ bool SPIRVInstructionSelector::selectAtomicStore(MachineInstr &I) const { MemSem |= static_cast<uint32_t>(SPIRV::MemorySemantics::Volatile); uint32_t Sem = getMemSemanticsWithStorageClass(STI.getTargetTriple(), MemSem, StorageClass); - Register MemSemReg = buildI32Constant(Sem, I); + Register MemSemReg = buildI32ConstantInEntryBlock(Sem, I); MachineIRBuilder MIRBuilder(I); if (PointeeType.isTypePtr()) { @@ -2391,7 +2391,7 @@ bool SPIRVInstructionSelector::selectMaskedGather(Register ResVReg, const uint32_t Alignment = I.getOperand(3).getImm(); const Register MaskReg = I.getOperand(4).getReg(); const Register PassthruReg = I.getOperand(5).getReg(); - const Register AlignmentReg = buildI32Constant(Alignment, I); + const Register AlignmentReg = buildI32ConstantInEntryBlock(Alignment, I); MachineBasicBlock &BB = *I.getParent(); auto MIB = @@ -2418,7 +2418,7 @@ bool SPIRVInstructionSelector::selectMaskedScatter(MachineInstr &I) const { const Register PtrsReg = I.getOperand(2).getReg(); const uint32_t Alignment = I.getOperand(3).getImm(); const Register MaskReg = I.getOperand(4).getReg(); - const Register AlignmentReg = buildI32Constant(Alignment, I); + const Register AlignmentReg = buildI32ConstantInEntryBlock(Alignment, I); MachineBasicBlock &BB = *I.getParent(); auto MIB = @@ -2615,14 +2615,14 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, uint32_t Scope = static_cast<uint32_t>( getMemScope(STI.getTargetTriple(), GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID())); - Register ScopeReg = buildI32Constant(Scope, I); + Register ScopeReg = buildI32ConstantInEntryBlock(Scope, I); Register Ptr = I.getOperand(1).getReg(); uint32_t ScSem = static_cast<uint32_t>( getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr))); AtomicOrdering AO = MemOp->getSuccessOrdering(); uint32_t OrderSem = static_cast<uint32_t>(getMemSemantics(AO)); - Register MemSemReg = buildI32Constant( + Register MemSemReg = buildI32ConstantInEntryBlock( getMemSemanticsWithStorageClass(STI.getTargetTriple(), OrderSem, ScSem), I); @@ -3709,12 +3709,12 @@ bool SPIRVInstructionSelector::selectBarrierInst(MachineInstr &I, // OpControlBarrier needs to also set Execution Scope if (WithGroupSync) { - Register ExecReg = buildI32Constant(SPIRV::Scope::Workgroup, I); + Register ExecReg = buildI32ConstantInEntryBlock(SPIRV::Scope::Workgroup, I); MI.addUse(ExecReg); } - Register ScopeReg = buildI32Constant(Scope, I); - Register MemSemReg = buildI32Constant(MemSem, I); + Register ScopeReg = buildI32ConstantInEntryBlock(Scope, I); + Register MemSemReg = buildI32ConstantInEntryBlock(MemSem, I); MI.addUse(ScopeReg).addUse(MemSemReg).constrainAllUses(TII, TRI, RBI); return true; @@ -6027,7 +6027,7 @@ bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg, SPIRVTypeInst IntPtrType = GR.getOrCreateSPIRVPointerType( LLVMIntType, MIRBuilder, SPIRV::StorageClass::StorageBuffer); - Register Zero = buildI32Constant(0, I); + Register Zero = buildI32ConstantInEntryBlock(0, I); Register PtrToCounter = MRI->createVirtualRegister(GR.getRegClass(IntPtrType)); @@ -6040,11 +6040,11 @@ bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg, // For UAV/SSBO counters, the scope is Device. The counter variable is not // used as a flag. So the memory semantics can be None. - Register Scope = buildI32Constant(SPIRV::Scope::Device, I); - Register Semantics = buildI32Constant(SPIRV::MemorySemantics::None, I); + Register Scope = buildI32ConstantInEntryBlock(SPIRV::Scope::Device, I); + Register Semantics = buildI32ConstantInEntryBlock(SPIRV::MemorySemantics::None, I); int64_t IncrVal = getIConstValSext(IncrReg, MRI); - Register Incr = buildI32Constant(static_cast<uint32_t>(IncrVal), I); + Register Incr = buildI32ConstantInEntryBlock(static_cast<uint32_t>(IncrVal), I); Register AtomicRes = MRI->createVirtualRegister(GR.getRegClass(ResType)); BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAtomicIAdd)) diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all_memory_barrier_with_group_sync.ll index b39c305b45a075..af0fe2f8b9b467 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all_memory_barrier_with_group_sync.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all_memory_barrier_with_group_sync.ll @@ -6,9 +6,9 @@ define void @test_all_memory_barrier_with_group_sync() #0 { entry: ; CHECK: %[[#TY:]] = OpTypeInt 32 0 + ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 2376 ; CHECK-DAG: %[[#EXEC_SCOPE:]] = OpConstant %[[#TY]] 2 ; CHECK-DAG: %[[#MEM_SCOPE:]] = OpConstant %[[#TY]] 1 - ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 2376 ; CHECK: OpControlBarrier %[[#EXEC_SCOPE]] %[[#MEM_SCOPE]] %[[#MEM_SEM]] call void @llvm.spv.all.memory.barrier.with.group.sync() ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/device_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/device_memory_barrier_with_group_sync.ll index 08eb0ed5706a51..614dfb636ed4c1 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/device_memory_barrier_with_group_sync.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/device_memory_barrier_with_group_sync.ll @@ -6,9 +6,9 @@ define void @test_device_memory_barrier_with_group_sync() #0 { entry: ; CHECK: %[[#TY:]] = OpTypeInt 32 0 + ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 2120 ; CHECK-DAG: %[[#EXEC_SCOPE:]] = OpConstant %[[#TY]] 2 ; CHECK-DAG: %[[#MEM_SCOPE:]] = OpConstant %[[#TY]] 1 - ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 2120 ; CHECK: OpControlBarrier %[[#EXEC_SCOPE]] %[[#MEM_SCOPE]] %[[#MEM_SEM]] call void @llvm.spv.device.memory.barrier.with.group.sync() ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier.ll index 987e7b57662c90..a045c8a00f4ed0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier.ll @@ -6,8 +6,8 @@ define void @test_group_memory_barrier() #0 { entry: ; CHECK: %[[#TY:]] = OpTypeInt 32 0 - ; CHECK-DAG: %[[#MEM_SCOPE:]] = OpConstant %[[#TY]] 2 ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 264 + ; CHECK-DAG: %[[#MEM_SCOPE:]] = OpConstant %[[#TY]] 2 ; CHECK: OpMemoryBarrier %[[#MEM_SCOPE]] %[[#MEM_SEM]] call void @llvm.spv.group.memory.barrier() ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll index 0ecd0a053ae3b9..3dcd21ef64be72 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll @@ -6,8 +6,8 @@ define void @test_group_memory_barrier_with_group_sync() #0 { entry: ; CHECK: %[[#TY:]] = OpTypeInt 32 0 - ; CHECK-DAG: %[[#EXEC_AND_MEM_SCOPE:]] = OpConstant %[[#TY]] 2 ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 264 + ; CHECK-DAG: %[[#EXEC_AND_MEM_SCOPE:]] = OpConstant %[[#TY]] 2 ; CHECK: OpControlBarrier %[[#EXEC_AND_MEM_SCOPE]] %[[#EXEC_AND_MEM_SCOPE]] %[[#MEM_SEM]] call void @llvm.spv.group.memory.barrier.with.group.sync() ret void `````````` </details> https://github.com/llvm/llvm-project/pull/234291 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
