llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Hongyu Chen (XChy) <details> <summary>Changes</summary> This patch supports packed slide intrinsics using funnel shifts. On RV32, the 64-bit funnel shift expands into select instructions, so it involves branches. I will try to merge these branches for better codegen in a follow-up. --- Patch is 39.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/234629.diff 5 Files Affected: - (modified) clang/lib/Headers/riscv_packed_simd.h (+44) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+391) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+132) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+90) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+204) ``````````diff diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index c91cf66d0b31a..37cbecf286e1f 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -179,6 +179,24 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return __builtin_elementwise_fshr(__rs1, __rd, (ty)__shamt); \ } +#define __packed_slideupx(name, ty, bits_ty, log2_elt_bits) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \ + unsigned __rs2) { \ + bits_ty __bits = __builtin_elementwise_fshl( \ + __builtin_bit_cast(bits_ty, __rd), __builtin_bit_cast(bits_ty, __rs1), \ + (bits_ty)__rs2 << (log2_elt_bits)); \ + return __builtin_bit_cast(ty, __bits); \ + } + +#define __packed_slidedownx(name, ty, bits_ty, log2_elt_bits) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1, \ + unsigned __rs2) { \ + bits_ty __bits = __builtin_elementwise_fshr( \ + __builtin_bit_cast(bits_ty, __rs1), __builtin_bit_cast(bits_ty, __rd), \ + (bits_ty)__rs2 << (log2_elt_bits)); \ + return __builtin_bit_cast(ty, __bits); \ + } + #define __packed_widen_convert(name, rty, ty) \ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \ return __builtin_convertvector(__rs1, rty); \ @@ -1446,6 +1464,30 @@ __packed_slide1(pslide1down_u16x4, uint16x4_t, uint16_t, 1, 2, 3, 4) __packed_slide1(pslide1down_i32x2, int32x2_t, int32_t, 1, 2) __packed_slide1(pslide1down_u32x2, uint32x2_t, uint32_t, 1, 2) +/* Packed Slide (32-bit) */ +__packed_slideupx(pslideupx_i8x4, int8x4_t, uint32_t, 3) +__packed_slideupx(pslideupx_u8x4, uint8x4_t, uint32_t, 3) +__packed_slideupx(pslideupx_i16x2, int16x2_t, uint32_t, 4) +__packed_slideupx(pslideupx_u16x2, uint16x2_t, uint32_t, 4) +__packed_slidedownx(pslidedownx_i8x4, int8x4_t, uint32_t, 3) +__packed_slidedownx(pslidedownx_u8x4, uint8x4_t, uint32_t, 3) +__packed_slidedownx(pslidedownx_i16x2, int16x2_t, uint32_t, 4) +__packed_slidedownx(pslidedownx_u16x2, uint16x2_t, uint32_t, 4) + +/* Packed Slide (64-bit) */ +__packed_slideupx(pslideupx_i8x8, int8x8_t, uint64_t, 3) +__packed_slideupx(pslideupx_u8x8, uint8x8_t, uint64_t, 3) +__packed_slideupx(pslideupx_i16x4, int16x4_t, uint64_t, 4) +__packed_slideupx(pslideupx_u16x4, uint16x4_t, uint64_t, 4) +__packed_slideupx(pslideupx_i32x2, int32x2_t, uint64_t, 5) +__packed_slideupx(pslideupx_u32x2, uint32x2_t, uint64_t, 5) +__packed_slidedownx(pslidedownx_i8x8, int8x8_t, uint64_t, 3) +__packed_slidedownx(pslidedownx_u8x8, uint8x8_t, uint64_t, 3) +__packed_slidedownx(pslidedownx_i16x4, int16x4_t, uint64_t, 4) +__packed_slidedownx(pslidedownx_u16x4, uint16x4_t, uint64_t, 4) +__packed_slidedownx(pslidedownx_i32x2, int32x2_t, uint64_t, 5) +__packed_slidedownx(pslidedownx_u32x2, uint32x2_t, uint64_t, 5) + /* Packed Subvector Extract */ __packed_subvector_extract8(pget_i8x8_i8x4, int8x4_t, int8x8_t) __packed_subvector_extract8(pget_u8x8_u8x4, uint8x4_t, uint8x8_t) @@ -1647,6 +1689,8 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_cls #undef __packed_slx #undef __packed_srx +#undef __packed_slideupx +#undef __packed_slidedownx #undef __packed_widen_convert #undef __packed_widen_binary_op #undef __packed_widen_binary_acc_op diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 2233e5835ea1e..ef479a04af5dc 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -10224,3 +10224,394 @@ int64_t test_pm2wsuba_x_i64(int64_t rd, int16x2_t rs1, int16x2_t rs2) { int64_t test_pm2waddasu_i64(int64_t rd, int16x2_t rs1, uint16x2_t rs2) { return __riscv_pm2waddasu_i64(rd, rs1, rs2); } + +/* Packed Slide (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pslideupx_i8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_i8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int8x4_t test_pslideupx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_i8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslideupx_u8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_u8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint8x4_t test_pslideupx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_u8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslideupx_i16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_i16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int16x2_t test_pslideupx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_i16x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslideupx_u16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslideupx_u16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshl.i32(i32 [[RD_COERCE]], i32 [[RS1_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint16x2_t test_pslideupx_u16x2(uint16x2_t rd, uint16x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_u16x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_i8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_i8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int8x4_t test_pslidedownx_i8x4(int8x4_t rd, int8x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_u8x4( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_u8x4( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint8x4_t test_pslidedownx_u8x4(uint8x4_t rd, uint8x4_t rs1, unsigned rs2) { + return __riscv_pslidedownx_u8x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_i16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_i16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +int16x2_t test_pslidedownx_i16x2(int16x2_t rd, int16x2_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i16x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pslidedownx_u16x2( +// RV32-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pslidedownx_u16x2( +// RV64-SAME: i32 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[SHL_I:%.*]] = shl i32 [[RS2]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.fshr.i32(i32 [[RS1_COERCE]], i32 [[RD_COERCE]], i32 [[SHL_I]]) +// RV64-NEXT: ret i32 [[TMP0]] +// +uint16x2_t test_pslidedownx_u16x2(uint16x2_t rd, uint16x2_t rs1, + unsigned rs2) { + return __riscv_pslidedownx_u16x2(rd, rs1, rs2); +} + +/* Packed Slide (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pslideupx_i8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_i8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int8x8_t test_pslideupx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) { + return __riscv_pslideupx_i8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_u8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_u8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint8x8_t test_pslideupx_u8x8(uint8x8_t rd, uint8x8_t rs1, unsigned rs2) { + return __riscv_pslideupx_u8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_i16x4( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_i16x4( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int16x4_t test_pslideupx_i16x4(int16x4_t rd, int16x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_i16x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_u16x4( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_u16x4( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 4 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint16x4_t test_pslideupx_u16x4(uint16x4_t rd, uint16x4_t rs1, unsigned rs2) { + return __riscv_pslideupx_u16x4(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_i32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_i32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int32x2_t test_pslideupx_i32x2(int32x2_t rd, int32x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_i32x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslideupx_u32x2( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslideupx_u32x2( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 5 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 [[RD_COERCE]], i64 [[RS1_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +uint32x2_t test_pslideupx_u32x2(uint32x2_t rd, uint32x2_t rs1, unsigned rs2) { + return __riscv_pslideupx_u32x2(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_i8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_i8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV64-NEXT: ret i64 [[TMP0]] +// +int8x8_t test_pslidedownx_i8x8(int8x8_t rd, int8x8_t rs1, unsigned rs2) { + return __riscv_pslidedownx_i8x8(rd, rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pslidedownx_u8x8( +// RV32-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV32-NEXT: [[SHL_I:%.*]] = shl nuw nsw i64 [[CONV_I]], 3 +// RV32-NEXT: [[TMP0:%.*]] = call i64 @llvm.fshr.i64(i64 [[RS1_COERCE]], i64 [[RD_COERCE]], i64 [[SHL_I]]) +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pslidedownx_u8x8( +// RV64-SAME: i64 noundef [[RD_COERCE:%.*]], i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[CONV_I:%.*]] = zext i32 [[RS2]] to i64 +// RV64-NEXT: [[SHL_I:%.*]] = shl n... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/234629 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
