================
@@ -0,0 +1,443 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 6
+; RUN: opt < %s -passes=vector-combine -verify-each -S -mtriple=x86_64--
-mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -passes=vector-combine -verify-each -S -mtriple=x86_64--
-mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -passes=vector-combine -verify-each -S -mtriple=x86_64--
-mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN: opt < %s -passes=vector-combine -verify-each -S -mtriple=x86_64--
-mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX512
+; REQUIRES: x86-registered-target
+
+target datalayout = "e-m:e-p:64:64-i64:64-n8:16:32:64-S128"
+
+; Legal mask vectors can also form a store narrower than 128 bits.
+define void @width64(ptr %p, <64 x i1> %x) #0 {
+; SSE-LABEL: define void @width64(
+; SSE-SAME: ptr [[P:%.*]], <64 x i1> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; SSE-NEXT: [[LO:%.*]] = shufflevector <64 x i1> [[X]], <64 x i1> poison,
<32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32
9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32
19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32
29, i32 30, i32 31>
+; SSE-NEXT: [[HI:%.*]] = shufflevector <64 x i1> [[X]], <64 x i1> poison,
<32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32
40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32
50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32
60, i32 61, i32 62, i32 63>
+; SSE-NEXT: [[P4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 4
+; SSE-NEXT: store <32 x i1> [[LO]], ptr [[P]], align 4
+; SSE-NEXT: store <32 x i1> [[HI]], ptr [[P4]], align 4
+; SSE-NEXT: ret void
+;
+; AVX2-LABEL: define void @width64(
+; AVX2-SAME: ptr [[P:%.*]], <64 x i1> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; AVX2-NEXT: [[LO:%.*]] = shufflevector <64 x i1> [[X]], <64 x i1> poison,
<32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32
9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32
19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32
29, i32 30, i32 31>
+; AVX2-NEXT: [[HI:%.*]] = shufflevector <64 x i1> [[X]], <64 x i1> poison,
<32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32
40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32
50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32
60, i32 61, i32 62, i32 63>
+; AVX2-NEXT: [[P4:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 4
+; AVX2-NEXT: store <32 x i1> [[LO]], ptr [[P]], align 4
+; AVX2-NEXT: store <32 x i1> [[HI]], ptr [[P4]], align 4
+; AVX2-NEXT: ret void
+;
+; AVX512-LABEL: define void @width64(
+; AVX512-SAME: ptr [[P:%.*]], <64 x i1> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; AVX512-NEXT: store <64 x i1> [[X]], ptr [[P]], align 4
+; AVX512-NEXT: ret void
+;
+ %lo = shufflevector <64 x i1> %x, <64 x i1> poison, <32 x i32> <i32 0, i32
1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32
12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32
22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ %hi = shufflevector <64 x i1> %x, <64 x i1> poison, <32 x i32> <i32 32, i32
33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32
43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32
53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32
63>
+ %p4 = getelementptr inbounds i8, ptr %p, i64 4
+ store <32 x i1> %lo, ptr %p, align 4
+ store <32 x i1> %hi, ptr %p4, align 4
+ ret void
+}
+
+; Concatenating the two halves folds to %x, so no shuffle is charged.
+; This also works with noimplicitfloat and drops invariant.group metadata.
+; The preferred width prevents joining the following 128-bit store.
+define void @width128(ptr %p, <4 x float> %x, <4 x float> %y) #3 {
+; CHECK-LABEL: define void @width128(
+; CHECK-SAME: ptr [[P:%.*]], <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]])
#[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: [[P16:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 16
+; CHECK-NEXT: store <4 x float> [[X]], ptr [[P]], align 4
+; CHECK-NEXT: store <4 x float> [[Y]], ptr [[P16]], align 4
+; CHECK-NEXT: ret void
+;
+ %lo = shufflevector <4 x float> %x, <4 x float> poison, <2 x i32> <i32 0,
i32 1>
+ %hi = shufflevector <4 x float> %x, <4 x float> poison, <2 x i32> <i32 2,
i32 3>
+ %p16 = getelementptr inbounds i8, ptr %p, i64 16
+ store <2 x float> %lo, ptr %p, align 4, !invariant.group !1
+ %p8 = getelementptr inbounds i8, ptr %p, i64 8
+ store <2 x float> %hi, ptr %p8, align 4, !invariant.group !1
+ store <4 x float> %y, ptr %p16, align 4
+ ret void
+}
+
+; A folded concatenation is profitable for code size too.
+; A 256-bit store still requires target support and a sufficient preferred
width.
+define void @width256(ptr %p, <8 x float> %x) #2 {
+; SSE-LABEL: define void @width256(
+; SSE-SAME: ptr [[P:%.*]], <8 x float> [[X:%.*]]) #[[ATTR2:[0-9]+]] {
+; SSE-NEXT: [[LO:%.*]] = shufflevector <8 x float> [[X]], <8 x float>
poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT: [[HI:%.*]] = shufflevector <8 x float> [[X]], <8 x float>
poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+; SSE-NEXT: [[P16:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 16
+; SSE-NEXT: store <4 x float> [[LO]], ptr [[P]], align 4
+; SSE-NEXT: store <4 x float> [[HI]], ptr [[P16]], align 4
+; SSE-NEXT: ret void
+;
+; AVX2-LABEL: define void @width256(
+; AVX2-SAME: ptr [[P:%.*]], <8 x float> [[X:%.*]]) #[[ATTR2:[0-9]+]] {
+; AVX2-NEXT: store <8 x float> [[X]], ptr [[P]], align 4
+; AVX2-NEXT: ret void
+;
+; AVX512-LABEL: define void @width256(
+; AVX512-SAME: ptr [[P:%.*]], <8 x float> [[X:%.*]]) #[[ATTR2:[0-9]+]] {
+; AVX512-NEXT: store <8 x float> [[X]], ptr [[P]], align 4
+; AVX512-NEXT: ret void
+;
+ %lo = shufflevector <8 x float> %x, <8 x float> poison, <4 x i32> <i32 0,
i32 1, i32 2, i32 3>
+ %hi = shufflevector <8 x float> %x, <8 x float> poison, <4 x i32> <i32 4,
i32 5, i32 6, i32 7>
+ %p16 = getelementptr inbounds i8, ptr %p, i64 16
+ store <4 x float> %lo, ptr %p, align 4
+ store <4 x float> %hi, ptr %p16, align 4
+ ret void
+}
+
+; A 512-bit store requires both target support and a sufficient preferred
width.
+define void @width512(ptr %p, <16 x float> %x) #4 {
+; SSE-LABEL: define void @width512(
+; SSE-SAME: ptr [[P:%.*]], <16 x float> [[X:%.*]]) #[[ATTR3:[0-9]+]] {
+; SSE-NEXT: [[LO:%.*]] = shufflevector <16 x float> [[X]], <16 x float>
poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; SSE-NEXT: [[HI:%.*]] = shufflevector <16 x float> [[X]], <16 x float>
poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; SSE-NEXT: [[P32:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 32
+; SSE-NEXT: store <8 x float> [[LO]], ptr [[P]], align 4
+; SSE-NEXT: store <8 x float> [[HI]], ptr [[P32]], align 4
+; SSE-NEXT: ret void
+;
+; AVX2-LABEL: define void @width512(
+; AVX2-SAME: ptr [[P:%.*]], <16 x float> [[X:%.*]]) #[[ATTR3:[0-9]+]] {
+; AVX2-NEXT: [[LO:%.*]] = shufflevector <16 x float> [[X]], <16 x float>
poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; AVX2-NEXT: [[HI:%.*]] = shufflevector <16 x float> [[X]], <16 x float>
poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; AVX2-NEXT: [[P32:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 32
+; AVX2-NEXT: store <8 x float> [[LO]], ptr [[P]], align 4
+; AVX2-NEXT: store <8 x float> [[HI]], ptr [[P32]], align 4
+; AVX2-NEXT: ret void
+;
+; AVX512-LABEL: define void @width512(
+; AVX512-SAME: ptr [[P:%.*]], <16 x float> [[X:%.*]]) #[[ATTR3:[0-9]+]] {
+; AVX512-NEXT: store <16 x float> [[X]], ptr [[P]], align 4
+; AVX512-NEXT: ret void
+;
+ %lo = shufflevector <16 x float> %x, <16 x float> poison, <8 x i32> <i32 0,
i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %hi = shufflevector <16 x float> %x, <16 x float> poison, <8 x i32> <i32 8,
i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %p32 = getelementptr inbounds i8, ptr %p, i64 32
+ store <8 x float> %lo, ptr %p, align 4
+ store <8 x float> %hi, ptr %p32, align 4
+ ret void
+}
+
+; Being below the width limit does not make a 192-bit vector type legal.
+define void @illegal_width192(ptr %p, <6 x float> %x) #4 {
+; CHECK-LABEL: define void @illegal_width192(
+; CHECK-SAME: ptr [[P:%.*]], <6 x float> [[X:%.*]]) #[[ATTR3:[0-9]+]] {
+; CHECK-NEXT: [[LO:%.*]] = shufflevector <6 x float> [[X]], <6 x float>
poison, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: [[HI:%.*]] = shufflevector <6 x float> [[X]], <6 x float>
poison, <3 x i32> <i32 3, i32 4, i32 5>
+; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12
+; CHECK-NEXT: store <3 x float> [[LO]], ptr [[P]], align 4
----------------
Andarwinux wrote:
I think best as a TODO for now. This could be two follow-up: reshuffle non-pow2
stores into pow2 stores, and merge into one masked store when profitable.
https://github.com/llvm/llvm-project/pull/232587
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