Author: Q Date: 2026-10-23T16:47:15Z New Revision: a94e3ab36315be39fb0f30be2eda3458ee1f369a
URL: https://github.com/llvm/llvm-project/commit/a94e3ab36315be39fb0f30be2eda3458ee1f369a DIFF: https://github.com/llvm/llvm-project/commit/a94e3ab36315be39fb0f30be2eda3458ee1f369a.diff LOG: [Clang][RISCV][P-ext] Add Packed Widening Multiply Accumulate intrinsics (#226505) Add intrinsics, Clang builtins and SelectionDAG support for the packed widening multiply-accumulate operations. See https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-widening-multiply-accumulate. On RV32, the pwmacc.h family accumulates into the register pair holding rd. On RV64, the operations are lowered according to the spec decomposition table, using zip16p and the pmacc.w.h01/pmaccu.w.h01 forms, or pwcvtu.wh followed by pmaccsu.w.h00 for the signed-unsigned form. Added: Modified: clang/include/clang/Basic/BuiltinsRISCV.td clang/lib/CodeGen/TargetBuiltins/RISCV.cpp clang/lib/Headers/riscv_packed_simd.h clang/test/CodeGen/RISCV/rvp-intrinsics.c cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfoP.td llvm/test/CodeGen/RISCV/rvp-simd-64.ll Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 0a51ebdd3301d..704547a683004 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -408,6 +408,11 @@ def pm4add_i16x4 : RISCVBuiltin<"int64_t(_Vector<4, short>, _Vector<4, short>)"> def pm4addu_u16x4 : RISCVBuiltin<"uint64_t(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; def pm4addsu_i16x4 : RISCVBuiltin<"int64_t(_Vector<4, short>, _Vector<4, unsigned short>)">; +// Packed Widening Multiply Accumulate +def pwmacc_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, short>, _Vector<2, short>)">; +def pwmaccu_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def pwmaccsu_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, short>, _Vector<2, unsigned short>)">; + // Packed Multiplication with Widening Horizontal Addition (32-bit) def pm2wadd_i64 : RISCVBuiltin<"int64_t(_Vector<2, short>, _Vector<2, short>)">; def pm2wadd_x_i64 : RISCVBuiltin<"int64_t(_Vector<2, short>, _Vector<2, short>)">; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index eb38a20f32e28..0d6bc6c66c1a0 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1912,6 +1912,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; } + // Packed Widening Multiply Accumulate + case RISCV::BI__builtin_riscv_pwmacc_i32x2: + case RISCV::BI__builtin_riscv_pwmaccu_u32x2: + case RISCV::BI__builtin_riscv_pwmaccsu_i32x2: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_pwmacc_i32x2: + ID = Intrinsic::riscv_pwmacc_i32x2; + break; + case RISCV::BI__builtin_riscv_pwmaccu_u32x2: + ID = Intrinsic::riscv_pwmaccu_u32x2; + break; + case RISCV::BI__builtin_riscv_pwmaccsu_i32x2: + ID = Intrinsic::riscv_pwmaccsu_i32x2; + break; + } + + IntrinsicTypes = {ResultType, Ops[1]->getType()}; + break; + } + // Packed Multiplication with Widening Horizontal Addition and Accumulate. case RISCV::BI__builtin_riscv_pm2wadda_i64: case RISCV::BI__builtin_riscv_pm2wadda_x_i64: diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index e166308fd6058..88c330cf7761d 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -1197,7 +1197,12 @@ __packed_binary_builtin_mixed(pm4add_i16x4, int64_t, int16x4_t, int16x4_t, __bui __packed_binary_builtin_mixed(pm4addu_u16x4, uint64_t, uint16x4_t, uint16x4_t, __builtin_riscv_pm4addu_u16x4) __packed_binary_builtin_mixed(pm4addsu_i16x4, int64_t, int16x4_t, uint16x4_t, __builtin_riscv_pm4addsu_i16x4) -/* Packed Multiplication with Horizontal Addition and Accumulate (64-bit) */ +/* Packed Widening Multiply Accumulate */ +__packed_ternary_builtin_mixed(pwmacc_i32x2, int32x2_t, int16x2_t, int16x2_t, __builtin_riscv_pwmacc_i32x2) +__packed_ternary_builtin_mixed(pwmaccu_u32x2, uint32x2_t, uint16x2_t, uint16x2_t, __builtin_riscv_pwmaccu_u32x2) +__packed_ternary_builtin_mixed(pwmaccsu_i32x2, int32x2_t, int16x2_t, uint16x2_t, __builtin_riscv_pwmaccsu_i32x2) + + /* Packed Multiplication with Horizontal Addition and Accumulate (64-bit) */ static __inline__ int32x2_t __DEFAULT_FN_ATTRS __riscv_pm4adda_i8x8(int32x2_t __rd, int8x8_t __rs1, int8x8_t __rs2) { return (int32x2_t)((uint32x2_t)__rd + diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 7decad176c949..928520c11c0a4 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -10115,6 +10115,49 @@ uint32x2_t test_pslide1down_u32x2(uint32x2_t rd, uint32_t rs1) { return __riscv_pslide1down_u32x2(rd, rs1); } +/* Packed Widening Multiply Accumulate */ +// CHECK-LABEL: define dso_local i64 @test_pwmacc_i32x2( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pwmacc.i32x2.v2i32.v2i16(<2 x i32> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 +// CHECK-NEXT: ret i64 [[TMP4]] +// +int32x2_t test_pwmacc_i32x2(int32x2_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_pwmacc_i32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: define dso_local i64 @test_pwmaccu_u32x2( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pwmaccu.u32x2.v2i32.v2i16(<2 x i32> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 +// CHECK-NEXT: ret i64 [[TMP4]] +// +uint32x2_t test_pwmaccu_u32x2(uint32x2_t rd, uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwmaccu_u32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: define dso_local i64 @test_pwmaccsu_i32x2( +// CHECK-SAME: i64 noundef [[RD_COERCE:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pwmaccsu.i32x2.v2i32.v2i16(<2 x i32> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 +// CHECK-NEXT: ret i64 [[TMP4]] +// +int32x2_t test_pwmaccsu_i32x2(int32x2_t rd, int16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwmaccsu_i32x2(rd, rs1, rs2); +} + // CHECK-LABEL: define dso_local i64 @test_pm2wadd_i64( // CHECK-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 20947a723b1fc..134f2f5159807 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -4545,6 +4545,31 @@ int64_t test_pm4addsu_i16x4(int16x4_t rs1, uint16x4_t rs2) { return __riscv_pm4addsu_i16x4(rs1, rs2); } +// Packed Widening Multiply Accumulate. +// CHECK-LABEL: test_pwmacc_i32x2: +// RV32: pwmacc.h +// RV64: zip16p +// RV64: pmacc.w.h01 +int32x2_t test_pwmacc_i32x2(int32x2_t rd, int16x2_t rs1, int16x2_t rs2) { + return __riscv_pwmacc_i32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pwmaccu_u32x2: +// RV32: pwmaccu.h +// RV64: zip16p +// RV64: pmaccu.w.h01 +uint32x2_t test_pwmaccu_u32x2(uint32x2_t rd, uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwmaccu_u32x2(rd, rs1, rs2); +} + +// CHECK-LABEL: test_pwmaccsu_i32x2: +// RV32: pwmaccsu.h +// RV64: pwcvtu.wh +// RV64: pmaccsu.w.h00 +int32x2_t test_pwmaccsu_i32x2(int32x2_t rd, int16x2_t rs1, uint16x2_t rs2) { + return __riscv_pwmaccsu_i32x2(rd, rs1, rs2); +} + // Packed Byte Multiplication with Horizontal Addition and Accumulate. // CHECK-LABEL: test_pm4adda_i8x8: // RV32: pm4adda.b{{[[:space:]]}} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 79b7022d476de..397f0f4efa9b6 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -2395,6 +2395,19 @@ class RVPBinaryIntrinsic def int_riscv_pmaccsu_00 : RVPPackedMulPartsAccIntrinsic; def int_riscv_pmaccsu_11 : RVPPackedMulPartsAccIntrinsic; + // Packed Widening Multiply Accumulate. + // The pwmacc*/pwmaccsu* instructions are available on RV32. + // On RV64, these operations are synthesized using the instruction + // sequences specified by the P extension. + class RVPWideningMulAccIntrinsic + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, llvm_anyvector_ty, + LLVMMatchType<1>], + [IntrNoMem, IntrSpeculatable]>; + def int_riscv_pwmacc_i32x2 : RVPWideningMulAccIntrinsic; + def int_riscv_pwmaccu_u32x2 : RVPWideningMulAccIntrinsic; + def int_riscv_pwmaccsu_i32x2 : RVPWideningMulAccIntrinsic; + class RVPScalarMulPartsAccIntrinsic : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_anyvector_ty, diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 728e406c822b3..ebbcf93cce642 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12653,6 +12653,19 @@ static unsigned getRVPHorizontalMulOpcode(unsigned IntNo) { } } +static unsigned getRVPWideningMulAccOpcode(unsigned IntNo) { + switch (IntNo) { + default: + llvm_unreachable("Unexpected RISC-V packed pwmacc intrinsic"); + case Intrinsic::riscv_pwmacc_i32x2: + return RISCVISD::PWMACC_H; + case Intrinsic::riscv_pwmaccu_u32x2: + return RISCVISD::PWMACCU_H; + case Intrinsic::riscv_pwmaccsu_i32x2: + return RISCVISD::PWMACCSU_H; + } +} + static unsigned getRVPHorizontalMulAccOpcode(unsigned IntNo) { switch (IntNo) { default: @@ -13688,6 +13701,44 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(Opc, DL, VT, Rs1, Rs2); } + case Intrinsic::riscv_pwmacc_i32x2: + case Intrinsic::riscv_pwmaccu_u32x2: + case Intrinsic::riscv_pwmaccsu_i32x2: { + EVT VT = Op.getValueType(); + SDValue Acc = Op.getOperand(1); + SDValue Rs1 = Op.getOperand(2); + SDValue Rs2 = Op.getOperand(3); + + if (Subtarget.is64Bit()) { + // Per the spec decomposition table: a single zip16p puts the + // halfwords of Rs1 in the even elements and those of Rs2 in the odd + // elements (the su form uses the pwcvtu.wh spelling, zip16p with x0). + // pmacc.w.h01 then multiplies the even elements of the first source + // by the odd elements of the second source into rd. RV32 selects the + // pwmacc.h family on the register pair instead. + Rs1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16, Rs1, + DAG.getUNDEF(MVT::v2i16)); + Rs2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16, Rs2, + DAG.getUNDEF(MVT::v2i16)); + if (IntNo == Intrinsic::riscv_pwmaccsu_i32x2) { + SDValue Zero = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::v4i16, + DAG.getConstant(0, DL, XLenVT)); + Rs1 = DAG.getNode(RISCVISD::PZIP, DL, MVT::v4i16, Rs1, Zero); + Rs2 = DAG.getNode(RISCVISD::PZIP, DL, MVT::v4i16, Rs2, Zero); + return DAG.getNode(RISCVISD::PMACCSU_HALVES_00, DL, VT, Acc, Rs1, Rs2); + } + SDValue Zip = DAG.getNode(RISCVISD::PZIP, DL, MVT::v4i16, Rs1, Rs2); + unsigned Opc = IntNo == Intrinsic::riscv_pwmaccu_u32x2 + ? RISCVISD::PMACCU_HALVES_01 + : RISCVISD::PMACC_HALVES_01; + return DAG.getNode(Opc, DL, VT, Acc, Zip, Zip); + } + + // RV32 uses pwmacc.h/pwmaccsu.h on the 64-bit accumulator register + // pair, represented as a single v2i32 value. + return DAG.getNode(getRVPWideningMulAccOpcode(IntNo), DL, VT, Acc, Rs1, + Rs2); + } case Intrinsic::riscv_pm2wadd: case Intrinsic::riscv_pm2wadd_x: case Intrinsic::riscv_pm2waddu: diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 16eed1a1afb38..6c98848685b36 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -1993,6 +1993,18 @@ def riscv_pmaccsu_halves_00 def riscv_pmaccsu_halves_11 : RVSDNode<"PMACCSU_HALVES_11", SDT_RISCVWideningMulAccByHalves>; +// The pwmacc*/pwmaccsu* instructions accumulate into the 64-bit register +// pair holding rd, represented as a v2i32 on RV32. +def SDT_RISCVPackedWideningMulAccPair + : SDTypeProfile<1, 3, [SDTCisVT<0, v2i32>, SDTCisSameAs<0, 1>, + SDTCisVT<2, v2i16>, SDTCisSameAs<2, 3>]>; +def riscv_pwmacc_h : RVSDNode<"PWMACC_H", + SDT_RISCVPackedWideningMulAccPair>; +def riscv_pwmaccu_h : RVSDNode<"PWMACCU_H", + SDT_RISCVPackedWideningMulAccPair>; +def riscv_pwmaccsu_h : RVSDNode<"PWMACCSU_H", + SDT_RISCVPackedWideningMulAccPair>; + def SDT_RISCVWideningShiftLeft : SDTypeProfile<2, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, @@ -2800,6 +2812,17 @@ let append Predicates = [IsRV32] in { (v2i16 GPR:$rs1), (v2i16 GPR:$rs2))), (PM2WADDASU_H GPRPair:$rd, GPR:$rs1, GPR:$rs2)>; + // Packed widening multiply accumulate patterns. + def : Pat<(v2i32 (riscv_pwmacc_h (v2i32 GPRPair:$rd), + (v2i16 GPR:$rs1), (v2i16 GPR:$rs2))), + (PWMACC_H GPRPair:$rd, GPR:$rs1, GPR:$rs2)>; + def : Pat<(v2i32 (riscv_pwmaccu_h (v2i32 GPRPair:$rd), + (v2i16 GPR:$rs1), (v2i16 GPR:$rs2))), + (PWMACCU_H GPRPair:$rd, GPR:$rs1, GPR:$rs2)>; + def : Pat<(v2i32 (riscv_pwmaccsu_h (v2i32 GPRPair:$rd), + (v2i16 GPR:$rs1), (v2i16 GPR:$rs2))), + (PWMACCSU_H GPRPair:$rd, GPR:$rs1, GPR:$rs2)>; + // 8/16-bit bitreverse patterns // With Zbkb, brev8 reverses the bits within each byte directly; otherwise // reverse all bits then swap the bytes back. diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index e79a69131e7b8..8e190a181400f 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -8449,6 +8449,53 @@ define <2 x i32> @test_pmaccsu_h11_v2i32(<2 x i32> %rd, <4 x i16> %a, <4 x i16> ret <2 x i32> %r } +; Packed Widening Multiply Accumulate +define <2 x i32> @test_pwmacc_i32x2(<2 x i32> %rd, <2 x i16> %rs1, <2 x i16> %rs2) { +; RV32-LABEL: test_pwmacc_i32x2: +; RV32: # %bb.0: +; RV32-NEXT: pwmacc.h a0, a2, a3 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pwmacc_i32x2: +; RV64: # %bb.0: +; RV64-NEXT: zip16p a1, a1, a2 +; RV64-NEXT: pmacc.w.h01 a0, a1, a1 +; RV64-NEXT: ret + %res = call <2 x i32> @llvm.riscv.pwmacc.i32x2.v2i32.v2i16(<2 x i32> %rd, <2 x i16> %rs1, <2 x i16> %rs2) + ret <2 x i32> %res +} + +define <2 x i32> @test_pwmaccu_u32x2(<2 x i32> %rd, <2 x i16> %rs1, <2 x i16> %rs2) { +; RV32-LABEL: test_pwmaccu_u32x2: +; RV32: # %bb.0: +; RV32-NEXT: pwmaccu.h a0, a2, a3 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pwmaccu_u32x2: +; RV64: # %bb.0: +; RV64-NEXT: zip16p a1, a1, a2 +; RV64-NEXT: pmaccu.w.h01 a0, a1, a1 +; RV64-NEXT: ret + %res = call <2 x i32> @llvm.riscv.pwmaccu.u32x2.v2i32.v2i16(<2 x i32> %rd, <2 x i16> %rs1, <2 x i16> %rs2) + ret <2 x i32> %res +} + +define <2 x i32> @test_pwmaccsu_i32x2(<2 x i32> %rd, <2 x i16> %rs1, <2 x i16> %rs2) { +; RV32-LABEL: test_pwmaccsu_i32x2: +; RV32: # %bb.0: +; RV32-NEXT: pwmaccsu.h a0, a2, a3 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pwmaccsu_i32x2: +; RV64: # %bb.0: +; RV64-NEXT: pwcvtu.wh a2, a2 +; RV64-NEXT: pwcvtu.wh a1, a1 +; RV64-NEXT: pmaccsu.w.h00 a0, a1, a2 +; RV64-NEXT: ret + %res = call <2 x i32> @llvm.riscv.pwmaccsu.i32x2.v2i32.v2i16(<2 x i32> %rd, <2 x i16> %rs1, <2 x i16> %rs2) + ret <2 x i32> %res +} + define i64 @test_macc_w00_i64(i64 %rd, <2 x i32> %a, <2 x i32> %b) { ; RV32-LABEL: test_macc_w00_i64: ; RV32: # %bb.0: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
