Author: Shilei Tian Date: 2026-10-23T22:12:39-07:00 New Revision: f8da8e372c0700ffca674c0c72404a27d0149cf8
URL: https://github.com/llvm/llvm-project/commit/f8da8e372c0700ffca674c0c72404a27d0149cf8 DIFF: https://github.com/llvm/llvm-project/commit/f8da8e372c0700ffca674c0c72404a27d0149cf8.diff LOG: [AMDGPU] Remove XNACK from gfx12-5-generic (#233329) This affects downstream targets. Added: Modified: clang/test/Driver/hip-sanitize-options.hip llvm/lib/Target/AMDGPU/GCNFeatures.td llvm/test/CodeGen/AMDGPU/sad.ll Removed: ################################################################################ diff --git a/clang/test/Driver/hip-sanitize-options.hip b/clang/test/Driver/hip-sanitize-options.hip index 4c14df283f775..95a0308677d33 100644 --- a/clang/test/Driver/hip-sanitize-options.hip +++ b/clang/test/Driver/hip-sanitize-options.hip @@ -8,11 +8,6 @@ // RUN: -nogpuinc --rocm-path=%S/Inputs/rocm \ // RUN: %s 2>&1 | FileCheck -check-prefixes=NORDC %s -// RUN: %clang -### --target=x86_64-unknown-linux-gnu --offload-arch=gfx12-5-generic:xnack+ \ -// RUN: -fsanitize=address \ -// RUN: -nogpuinc --rocm-path=%S/Inputs/rocm \ -// RUN: %s 2>&1 | FileCheck -check-prefixes=NORDC %s - // RUN: %clang -### --target=x86_64-unknown-linux-gnu --offload-arch=gfx900:xnack+ \ // RUN: -fsanitize=address -fno-gpu-sanitize \ // RUN: -nogpuinc --rocm-path=%S/Inputs/rocm \ diff --git a/llvm/lib/Target/AMDGPU/GCNFeatures.td b/llvm/lib/Target/AMDGPU/GCNFeatures.td index a2760139eeebf..8a5d5d4c7c57d 100644 --- a/llvm/lib/Target/AMDGPU/GCNFeatures.td +++ b/llvm/lib/Target/AMDGPU/GCNFeatures.td @@ -2705,8 +2705,6 @@ def FeatureISAVersion12_5_Generic: FeatureSet< FeatureDataCacheLineSize128, FeatureRequiresInitialUnclausedVmem, FeatureNeedsTDMDrain, - FeatureXNACKOnOffModes, - FeatureSupportsXNACK, ])>; def FeatureISAVersion13 : FeatureSet< diff --git a/llvm/test/CodeGen/AMDGPU/sad.ll b/llvm/test/CodeGen/AMDGPU/sad.ll index 3898a58d8cd27..5e31f9e463355 100644 --- a/llvm/test/CodeGen/AMDGPU/sad.ll +++ b/llvm/test/CodeGen/AMDGPU/sad.ll @@ -35,13 +35,12 @@ define amdgpu_kernel void @v_sad_u32_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, ; ; GFX12-5-SDAG-LABEL: v_sad_u32_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1 ; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1 @@ -50,18 +49,17 @@ define amdgpu_kernel void @v_sad_u32_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, ; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1 @@ -71,7 +69,7 @@ define amdgpu_kernel void @v_sad_u32_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, ; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %t0 = select i1 %icmp0, i32 %a, i32 %b @@ -116,7 +114,6 @@ define amdgpu_kernel void @v_sad_u32_constant_pat1(ptr addrspace(1) %out, i32 %a ; ; GFX12-5-SDAG-LABEL: v_sad_u32_constant_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -134,7 +131,6 @@ define amdgpu_kernel void @v_sad_u32_constant_pat1(ptr addrspace(1) %out, i32 %a ; ; GFX12-5-GISEL-LABEL: v_sad_u32_constant_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -196,13 +192,12 @@ define amdgpu_kernel void @v_sad_u32_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, ; ; GFX12-5-SDAG-LABEL: v_sad_u32_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s1, s0 ; GFX12-5-SDAG-NEXT: s_max_u32 s0, s1, s0 @@ -211,29 +206,28 @@ define amdgpu_kernel void @v_sad_u32_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, ; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_sub_co_u32 s3, s1, s0 -; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX12-5-GISEL-NEXT: s_cselect_b32 s6, 1, 0 ; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s1 -; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s6, 0 ; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s3 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %sub0 = sub i32 %a, %b @@ -297,13 +291,12 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(ptr addrspace(1) %out, i ; ; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_sub_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1 ; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1 @@ -315,18 +308,17 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(ptr addrspace(1) %out, i ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_sub_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1 @@ -338,7 +330,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(ptr addrspace(1) %out, i ; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0 -; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %t0 = select i1 %icmp0, i32 %a, i32 %b @@ -401,13 +393,12 @@ define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i ; ; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_add_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1 @@ -419,18 +410,17 @@ define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0 -; GFX12-5-SDAG-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_add_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1 @@ -442,7 +432,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0 -; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %t0 = select i1 %icmp0, i32 %a, i32 %b @@ -507,13 +497,12 @@ define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i ; ; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_max_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_max_u32 s3, s0, s1 ; GFX12-5-SDAG-NEXT: s_min_u32 s0, s0, s1 @@ -524,18 +513,17 @@ define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_max_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1 @@ -547,7 +535,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i ; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0 ; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0 -; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %t0 = select i1 %icmp0, i32 %a, i32 %b @@ -613,13 +601,12 @@ define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i ; ; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_min_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1 ; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1 @@ -630,18 +617,17 @@ define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_min_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1 @@ -653,7 +639,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i ; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0 -; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %t0 = select i1 %icmp0, i32 %a, i32 %b @@ -722,49 +708,47 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(ptr addrspace(1) %out, i ; ; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_sub_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s1, s0 -; GFX12-5-SDAG-NEXT: s_max_u32 s4, s1, s0 +; GFX12-5-SDAG-NEXT: s_max_u32 s6, s1, s0 ; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s1 -; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s4, s3 +; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s6, s3 ; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GFX12-5-SDAG-NEXT: s_add_co_i32 s1, s3, s2 ; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_sub_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_sub_co_u32 s3, s1, s0 -; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX12-5-GISEL-NEXT: s_cselect_b32 s6, 1, 0 ; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s1 -; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s6, 0 ; GFX12-5-GISEL-NEXT: s_cselect_b32 s1, s0, s3 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s1, s2 ; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0 -; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %sub0 = sub i32 %a, %b @@ -831,13 +815,12 @@ define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out ; ; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_select_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_min_u32 s3, s1, s0 ; GFX12-5-SDAG-NEXT: s_max_u32 s0, s1, s0 @@ -849,31 +832,30 @@ define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_select_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_sub_co_u32 s3, s1, s0 -; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX12-5-GISEL-NEXT: s_cselect_b32 s6, 1, 0 ; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s1 -; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s6, 0 ; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s3 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s0, s2 ; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0 -; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %sub0 = sub i32 %a, %b @@ -944,68 +926,66 @@ define amdgpu_kernel void @v_sad_u32_vector_pat1(ptr addrspace(1) %out, <4 x i32 ; ; GFX12-5-SDAG-LABEL: v_sad_u32_vector_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x2 ; GFX12-5-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv ; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-5-SDAG-NEXT: s_min_u32 s4, s8, s12 -; GFX12-5-SDAG-NEXT: s_max_u32 s5, s8, s12 +; GFX12-5-SDAG-NEXT: s_min_u32 s6, s8, s12 +; GFX12-5-SDAG-NEXT: s_max_u32 s7, s8, s12 ; GFX12-5-SDAG-NEXT: s_min_u32 s8, s9, s13 ; GFX12-5-SDAG-NEXT: s_max_u32 s9, s9, s13 ; GFX12-5-SDAG-NEXT: s_min_u32 s12, s10, s14 ; GFX12-5-SDAG-NEXT: s_max_u32 s10, s10, s14 ; GFX12-5-SDAG-NEXT: s_min_u32 s13, s11, s15 ; GFX12-5-SDAG-NEXT: s_max_u32 s11, s11, s15 -; GFX12-5-SDAG-NEXT: s_sub_co_i32 s4, s5, s4 -; GFX12-5-SDAG-NEXT: s_sub_co_i32 s5, s9, s8 +; GFX12-5-SDAG-NEXT: s_sub_co_i32 s6, s7, s6 +; GFX12-5-SDAG-NEXT: s_sub_co_i32 s7, s9, s8 ; GFX12-5-SDAG-NEXT: s_sub_co_i32 s8, s11, s13 ; GFX12-5-SDAG-NEXT: s_sub_co_i32 s9, s10, s12 ; GFX12-5-SDAG-NEXT: s_add_co_i32 s8, s8, s3 ; GFX12-5-SDAG-NEXT: s_add_co_i32 s9, s9, s2 -; GFX12-5-SDAG-NEXT: s_add_co_i32 s4, s4, s0 -; GFX12-5-SDAG-NEXT: s_add_co_i32 s5, s5, s1 -; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s4 -; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s9 +; GFX12-5-SDAG-NEXT: s_add_co_i32 s6, s6, s0 +; GFX12-5-SDAG-NEXT: s_add_co_i32 s7, s7, s1 +; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s6 +; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s9 ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v3, s8 -; GFX12-5-SDAG-NEXT: global_store_b128 v4, v[0:3], s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b128 v4, v[0:3], s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_vector_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x2 ; GFX12-5-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv ; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12-5-GISEL-NEXT: s_max_u32 s4, s8, s12 -; GFX12-5-GISEL-NEXT: s_max_u32 s5, s9, s13 +; GFX12-5-GISEL-NEXT: s_max_u32 s6, s8, s12 +; GFX12-5-GISEL-NEXT: s_max_u32 s7, s9, s13 ; GFX12-5-GISEL-NEXT: s_max_u32 s16, s10, s14 ; GFX12-5-GISEL-NEXT: s_max_u32 s17, s11, s15 ; GFX12-5-GISEL-NEXT: s_min_u32 s8, s8, s12 ; GFX12-5-GISEL-NEXT: s_min_u32 s9, s9, s13 ; GFX12-5-GISEL-NEXT: s_min_u32 s10, s10, s14 ; GFX12-5-GISEL-NEXT: s_min_u32 s11, s11, s15 -; GFX12-5-GISEL-NEXT: s_sub_co_i32 s4, s4, s8 -; GFX12-5-GISEL-NEXT: s_sub_co_i32 s5, s5, s9 +; GFX12-5-GISEL-NEXT: s_sub_co_i32 s6, s6, s8 +; GFX12-5-GISEL-NEXT: s_sub_co_i32 s7, s7, s9 ; GFX12-5-GISEL-NEXT: s_sub_co_i32 s8, s16, s10 ; GFX12-5-GISEL-NEXT: s_sub_co_i32 s9, s17, s11 -; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s4, s0 -; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s5, s1 +; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s6, s0 +; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s7, s1 ; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s8, s2 ; GFX12-5-GISEL-NEXT: s_add_co_i32 s3, s9, s3 ; GFX12-5-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX12-5-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] -; GFX12-5-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b128 v4, v[0:3], s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt <4 x i32> %a, %b %t0 = select <4 x i1> %icmp0, <4 x i32> %a, <4 x i32> %b @@ -1089,40 +1069,38 @@ define amdgpu_kernel void @v_sad_u32_vector_pat2(ptr addrspace(1) %out, <4 x i32 ; ; GFX12-5-SDAG-LABEL: v_sad_u32_vector_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x2 ; GFX12-5-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv ; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-5-SDAG-NEXT: s_min_u32 s4, s8, s12 -; GFX12-5-SDAG-NEXT: s_max_u32 s5, s8, s12 +; GFX12-5-SDAG-NEXT: s_min_u32 s6, s8, s12 +; GFX12-5-SDAG-NEXT: s_max_u32 s7, s8, s12 ; GFX12-5-SDAG-NEXT: s_min_u32 s8, s9, s13 ; GFX12-5-SDAG-NEXT: s_max_u32 s9, s9, s13 ; GFX12-5-SDAG-NEXT: s_min_u32 s12, s10, s14 ; GFX12-5-SDAG-NEXT: s_max_u32 s10, s10, s14 ; GFX12-5-SDAG-NEXT: s_min_u32 s13, s11, s15 ; GFX12-5-SDAG-NEXT: s_max_u32 s11, s11, s15 -; GFX12-5-SDAG-NEXT: s_sub_co_i32 s4, s5, s4 -; GFX12-5-SDAG-NEXT: s_sub_co_i32 s5, s9, s8 +; GFX12-5-SDAG-NEXT: s_sub_co_i32 s6, s7, s6 +; GFX12-5-SDAG-NEXT: s_sub_co_i32 s7, s9, s8 ; GFX12-5-SDAG-NEXT: s_sub_co_i32 s8, s11, s13 ; GFX12-5-SDAG-NEXT: s_sub_co_i32 s9, s10, s12 ; GFX12-5-SDAG-NEXT: s_add_co_i32 s8, s8, s3 ; GFX12-5-SDAG-NEXT: s_add_co_i32 s9, s9, s2 -; GFX12-5-SDAG-NEXT: s_add_co_i32 s4, s4, s0 -; GFX12-5-SDAG-NEXT: s_add_co_i32 s5, s5, s1 -; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s4 -; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s9 +; GFX12-5-SDAG-NEXT: s_add_co_i32 s6, s6, s0 +; GFX12-5-SDAG-NEXT: s_add_co_i32 s7, s7, s1 +; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s6 +; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s9 ; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v3, s8 -; GFX12-5-SDAG-NEXT: global_store_b128 v4, v[0:3], s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b128 v4, v[0:3], s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_vector_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1210,7 +1188,6 @@ define amdgpu_kernel void @v_sad_u32_i16_pat1(ptr addrspace(1) %out, i16 %a, i16 ; ; GFX12-5-SDAG-LABEL: v_sad_u32_i16_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1231,7 +1208,6 @@ define amdgpu_kernel void @v_sad_u32_i16_pat1(ptr addrspace(1) %out, i16 %a, i16 ; ; GFX12-5-GISEL-LABEL: v_sad_u32_i16_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1307,14 +1283,12 @@ define amdgpu_kernel void @v_sad_u32_i16_pat2(ptr addrspace(1) %out) { ; ; GFX12-5-SDAG-LABEL: v_sad_u32_i16_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: global_load_u16 v0, v[0:1], off scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv -; GFX12-5-SDAG-NEXT: s_wait_xcnt 0x0 ; GFX12-5-SDAG-NEXT: global_load_u16 v2, v[0:1], off scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-SDAG-NEXT: global_load_u16 v3, v[0:1], off scope:SCOPE_SYS @@ -1333,14 +1307,12 @@ define amdgpu_kernel void @v_sad_u32_i16_pat2(ptr addrspace(1) %out) { ; ; GFX12-5-GISEL-LABEL: v_sad_u32_i16_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: global_load_u16 v0, v[0:1], off scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv -; GFX12-5-GISEL-NEXT: s_wait_xcnt 0x0 ; GFX12-5-GISEL-NEXT: global_load_u16 v2, v[0:1], off scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-GISEL-NEXT: global_load_u16 v3, v[0:1], off scope:SCOPE_SYS @@ -1415,7 +1387,6 @@ define amdgpu_kernel void @v_sad_u32_i8_pat1(ptr addrspace(1) %out, i8 %a, i8 %b ; ; GFX12-5-SDAG-LABEL: v_sad_u32_i8_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1436,7 +1407,6 @@ define amdgpu_kernel void @v_sad_u32_i8_pat1(ptr addrspace(1) %out, i8 %a, i8 %b ; ; GFX12-5-GISEL-LABEL: v_sad_u32_i8_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1514,14 +1484,12 @@ define amdgpu_kernel void @v_sad_u32_i8_pat2(ptr addrspace(1) %out) { ; ; GFX12-5-SDAG-LABEL: v_sad_u32_i8_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: global_load_u8 v0, v[0:1], off scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv -; GFX12-5-SDAG-NEXT: s_wait_xcnt 0x0 ; GFX12-5-SDAG-NEXT: global_load_u8 v2, v[0:1], off scope:SCOPE_SYS ; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-SDAG-NEXT: global_load_u8 v3, v[0:1], off scope:SCOPE_SYS @@ -1537,14 +1505,12 @@ define amdgpu_kernel void @v_sad_u32_i8_pat2(ptr addrspace(1) %out) { ; ; GFX12-5-GISEL-LABEL: v_sad_u32_i8_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: global_load_u8 v0, v[0:1], off scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv -; GFX12-5-GISEL-NEXT: s_wait_xcnt 0x0 ; GFX12-5-GISEL-NEXT: global_load_u8 v2, v[0:1], off scope:SCOPE_SYS ; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-5-GISEL-NEXT: global_load_u8 v3, v[0:1], off scope:SCOPE_SYS @@ -1620,7 +1586,6 @@ define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext % ; ; GFX12-5-SDAG-LABEL: s_sad_u32_i8_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1641,7 +1606,6 @@ define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext % ; ; GFX12-5-GISEL-LABEL: s_sad_u32_i8_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE @@ -1710,45 +1674,43 @@ define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(ptr addrspace(1) % ; ; GFX12-5-SDAG-LABEL: v_sad_u32_mismatched_operands_pat1: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-5-SDAG-NEXT: s_max_u32 s4, s0, s1 +; GFX12-5-SDAG-NEXT: s_max_u32 s6, s0, s1 ; GFX12-5-SDAG-NEXT: s_cmp_le_u32 s0, s1 ; GFX12-5-SDAG-NEXT: s_cselect_b32 s0, s0, s3 ; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s4, s0 +; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s6, s0 ; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 -; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_mismatched_operands_pat1: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12-5-GISEL-NEXT: s_max_u32 s4, s0, s1 +; GFX12-5-GISEL-NEXT: s_max_u32 s6, s0, s1 ; GFX12-5-GISEL-NEXT: s_cmp_le_u32 s0, s1 ; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s3 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s4, s0 +; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s6, s0 ; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %t0 = select i1 %icmp0, i32 %a, i32 %b @@ -1799,42 +1761,40 @@ define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat2(ptr addrspace(1) % ; ; GFX12-5-SDAG-LABEL: v_sad_u32_mismatched_operands_pat2: ; GFX12-5-SDAG: ; %bb.0: -; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-SDAG-NEXT: v_nop ; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-SDAG-NEXT: s_clause 0x1 ; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv -; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s0, s3 ; GFX12-5-SDAG-NEXT: v_sub_co_u32 v0, s0, s1, s0 ; GFX12-5-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-5-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, s3, s0 ; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0 -; GFX12-5-SDAG-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-SDAG-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-SDAG-NEXT: s_endpgm ; ; GFX12-5-GISEL-LABEL: v_sad_u32_mismatched_operands_pat2: ; GFX12-5-GISEL: ; %bb.0: -; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX12-5-GISEL-NEXT: v_nop ; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX12-5-GISEL-NEXT: s_clause 0x1 ; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv -; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv +; GFX12-5-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-5-GISEL-NEXT: s_sub_co_u32 s1, s1, s0 -; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX12-5-GISEL-NEXT: s_cselect_b32 s6, 1, 0 ; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s3 -; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s6, 0 ; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s1 ; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2 ; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX12-5-GISEL-NEXT: s_endpgm %icmp0 = icmp ugt i32 %a, %b %sub0 = sub i32 %a, %d _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
