Author: Vicky Nguyen Date: 2026-10-30T20:20:21-07:00 New Revision: 23b5e66b83f0fa5ee8a8178a2bca740130111b6e
URL: https://github.com/llvm/llvm-project/commit/23b5e66b83f0fa5ee8a8178a2bca740130111b6e DIFF: https://github.com/llvm/llvm-project/commit/23b5e66b83f0fa5ee8a8178a2bca740130111b6e.diff LOG: [clang][CIR] Add tests for SVE2 svrecpe intrinsics (#236314) Tests for SVE2 svrecpe (https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svrecpe). Port: `clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_recpe.c` to `clang/test/CodeGen/AArch64/sve2/recpe.c` Part of https://github.com/llvm/llvm-project/issues/223963. Added: clang/test/CodeGen/AArch64/sve2/recpe.c Modified: Removed: clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_recpe.c ################################################################################ diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_recpe.c b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_recpe.c deleted file mode 100644 index 6d189f8d6fe9b8..00000000000000 --- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_recpe.c +++ /dev/null @@ -1,67 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK - -// REQUIRES: aarch64-registered-target - -#include <arm_sve.h> - -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 -#endif - -// CHECK-LABEL: @test_svrecpe_u32_z( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z18test_svrecpe_u32_zu10__SVBool_tu12__SVUint32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] -// -svuint32_t test_svrecpe_u32_z(svbool_t pg, svuint32_t op) -{ - return SVE_ACLE_FUNC(svrecpe,_u32,_z,)(pg, op); -} - -// CHECK-LABEL: @test_svrecpe_u32_m( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z18test_svrecpe_u32_mu12__SVUint32_tu10__SVBool_tS_( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] -// -svuint32_t test_svrecpe_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) -{ - return SVE_ACLE_FUNC(svrecpe,_u32,_m,)(inactive, pg, op); -} - -// CHECK-LABEL: @test_svrecpe_u32_x( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z18test_svrecpe_u32_xu10__SVBool_tu12__SVUint32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]] -// -svuint32_t test_svrecpe_u32_x(svbool_t pg, svuint32_t op) -{ - return SVE_ACLE_FUNC(svrecpe,_u32,_x,)(pg, op); -} diff --git a/clang/test/CodeGen/AArch64/sve2/recpe.c b/clang/test/CodeGen/AArch64/sve2/recpe.c new file mode 100644 index 00000000000000..1b185c436fb66c --- /dev/null +++ b/clang/test/CodeGen/AArch64/sve2/recpe.c @@ -0,0 +1,71 @@ +// REQUIRES: aarch64-registered-target + +// DEFINE: %{optimize} = opt -passes=mem2reg -S + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -target-feature +sve2 -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -target-feature +sve2 -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -target-feature +sve2 -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -target-feature +sve2 -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -target-feature +sve2 -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %} + +// RUN: %clang_cc1_cg_arm64_sve -target-feature +sve2 -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -target-feature +sve2 -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -target-feature +sve2 -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM + +//============================================================================= +// NOTES +// +// Tests for SVE2 RECPE intrinsics +//============================================================================= + +#include <arm_sve.h> + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// C-LABEL: @test_svrecpe_u32_z( +// CPP-LABEL: @_Z18test_svrecpe_u32_zu10__SVBool_tu12__SVUint32_t( +svuint32_t test_svrecpe_u32_z(svbool_t pg, svuint32_t op) +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : (!cir.vector<[16] x !cir.int<u, 1>>) -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: cir.call_llvm_intrinsic "aarch64.sve.urecpe" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !cir.int<u, 1>>, !cir.vector<[4] x !u32i>) -> !cir.vector<[4] x !u32i> + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[PG4:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[PG4]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret <vscale x 4 x i32> [[RES]] + return SVE_ACLE_FUNC(svrecpe,_u32,_z,)(pg, op); +} + +// C-LABEL: @test_svrecpe_u32_m( +// CPP-LABEL: @_Z18test_svrecpe_u32_mu12__SVUint32_tu10__SVBool_tS_( +svuint32_t test_svrecpe_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : (!cir.vector<[16] x !cir.int<u, 1>>) -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: cir.call_llvm_intrinsic "aarch64.sve.urecpe" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !cir.int<u, 1>>, !cir.vector<[4] x !u32i>) -> !cir.vector<[4] x !u32i> + +// LLVM-SAME: <vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[PG4:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> [[INACTIVE]], <vscale x 4 x i1> [[PG4]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret <vscale x 4 x i32> [[RES]] + return SVE_ACLE_FUNC(svrecpe,_u32,_m,)(inactive, pg, op); +} + +// C-LABEL: @test_svrecpe_u32_x( +// CPP-LABEL: @_Z18test_svrecpe_u32_xu10__SVBool_tu12__SVUint32_t( +svuint32_t test_svrecpe_u32_x(svbool_t pg, svuint32_t op) +{ +// CIR: cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : (!cir.vector<[16] x !cir.int<u, 1>>) -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: cir.call_llvm_intrinsic "aarch64.sve.urecpe" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !cir.int<u, 1>>, !cir.vector<[4] x !u32i>) -> !cir.vector<[4] x !u32i> + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[PG4:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[PG4]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret <vscale x 4 x i32> [[RES]] + return SVE_ACLE_FUNC(svrecpe,_u32,_x,)(pg, op); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
