================
@@ -13847,6 +13867,59 @@ SDValue
RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
: RISCVISD::PM4ADDA;
return DAG.getNode(AccOpc, DL, MVT::i64, Rd, A, B);
}
+ case Intrinsic::riscv_pm2adda:
+ case Intrinsic::riscv_pm2adda_x:
+ case Intrinsic::riscv_pm2addau:
+ case Intrinsic::riscv_pmq2adda:
+ case Intrinsic::riscv_pmqr2adda:
+ case Intrinsic::riscv_pm2suba:
+ case Intrinsic::riscv_pm2suba_x:
+ case Intrinsic::riscv_pm2addasu: {
+
+ MVT VT = Op.getSimpleValueType();
+ SDValue Rd = Op.getOperand(1);
+ SDValue Rs1 = Op.getOperand(2);
+ SDValue Rs2 = Op.getOperand(3);
+ unsigned Opc = getRVPMulAddAccOpcode(IntNo);
+
+ if (VT == MVT::i32)
+ return DAG.getNode(Opc, DL, MVT::i32, Rd, Rs1, Rs2);
+
+ if (VT == MVT::v2i32) {
+ if (Subtarget.is64Bit())
+ return DAG.getNode(Opc, DL, MVT::v2i32, Rd, Rs1, Rs2);
+
+ auto [Rs1Lo, Rs1Hi] = DAG.SplitVector(Rs1, DL);
+ auto [Rs2Lo, Rs2Hi] = DAG.SplitVector(Rs2, DL);
+ SDValue RdLo = DAG.getExtractVectorElt(DL, MVT::i32, Rd, 0);
+ SDValue RdHi = DAG.getExtractVectorElt(DL, MVT::i32, Rd, 1);
+ SDValue Lo = DAG.getNode(Opc, DL, MVT::i32, RdLo, Rs1Lo, Rs2Lo);
+ SDValue Hi = DAG.getNode(Opc, DL, MVT::i32, RdHi, Rs1Hi, Rs2Hi);
+ return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
+ }
+
+ assert(Subtarget.is64Bit() && VT == MVT::i64 &&
+ "Unexpected packed multiply-horizontal-add-accumulate result");
+ return DAG.getNode(Opc, DL, MVT::i64, Rd, Rs1, Rs2);
+ }
+ case Intrinsic::riscv_pm4adda:
+ case Intrinsic::riscv_pm4addau:
+ case Intrinsic::riscv_pm4addasu: {
+
+ MVT VT = Op.getSimpleValueType();
+ SDValue Rd = Op.getOperand(1);
+ SDValue Rs1 = Op.getOperand(2);
+ SDValue Rs2 = Op.getOperand(3);
+ unsigned Opc = IntNo == Intrinsic::riscv_pm4addau ? RISCVISD::PM4ADDAU
+ : IntNo == Intrinsic::riscv_pm4addasu ? RISCVISD::PM4ADDASU
+ : RISCVISD::PM4ADDA;
+
+ if (VT == MVT::i32)
----------------
topperc wrote:
Is this case only possible on RV32?
https://github.com/llvm/llvm-project/pull/236303
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