Changeset: 6de39e1794c0 for MonetDB
URL: http://dev.monetdb.org/hg/MonetDB?cmd=changeset;node=6de39e1794c0
Modified Files:
monetdb5/modules/mal/01_batcalc.mal
monetdb5/modules/mal/01_batcalc.mal.sh
monetdb5/modules/mal/01_calc.mal
monetdb5/modules/mal/01_calc.mal.sh
Branch: rdf
Log Message:
Fix up generated files after various merges.
diffs (truncated from 2671 to 300 lines):
diff --git a/monetdb5/modules/mal/01_batcalc.mal
b/monetdb5/modules/mal/01_batcalc.mal
--- a/monetdb5/modules/mal/01_batcalc.mal
+++ b/monetdb5/modules/mal/01_batcalc.mal
@@ -1423,6 +1423,7 @@ pattern *(v:flt,b:bat[:flt],s:bat[:oid])
address CMDbatMULenlarge
comment "Return V * B with candidates list, guarantee no overflow by returning
larger type";
+
pattern +(b1:bat[:oid],b2:bat[:oid]) :bat[:oid]
address CMDbatADDsignal
comment "Return B1 + B2, signal error on overflow [RDF only]";
@@ -21148,6 +21149,18 @@ pattern str_noerror(b:bat[:str],s:bat[:o
address CMDconvert_str
comment "cast from str to str with candidates list";
+pattern ifthenelse(v:bit, b1:bat[:any_1], b2:bat[:any_1]) :bat[:any_1]
+address CMDifthen
+comment "If-then-else operation to assemble a conditional result";
+
+pattern ifthenelse(v:bit, v1:any_1, b2:bat[:any_1]) :bat[:any_1]
+address CMDifthen
+comment "If-then-else operation to assemble a conditional result";
+
+pattern ifthenelse(v:bit, b1:bat[:any_1], v2:any_1) :bat[:any_1]
+address CMDifthen
+comment "If-then-else operation to assemble a conditional result";
+
pattern ifthenelse(b:bat[:bit], v1:any_1, v2:any_1) :bat[:any_1]
address CMDifthen
comment "If-then-else operation to assemble a conditional result";
diff --git a/monetdb5/modules/mal/01_batcalc.mal.sh
b/monetdb5/modules/mal/01_batcalc.mal.sh
--- a/monetdb5/modules/mal/01_batcalc.mal.sh
+++ b/monetdb5/modules/mal/01_batcalc.mal.sh
@@ -146,6 +146,50 @@ EOF
echo
done
+for func in +:ADD -:SUB; do
+ name=${func#*:}
+ op=${func%:*}
+ cat <<EOF
+pattern $op(b1:bat[:oid],b2:bat[:oid]) :bat[:oid]
+address CMDbat${name}signal
+comment "Return B1 $op B2, signal error on overflow [RDF only]";
+pattern $op(b1:bat[:oid],b2:bat[:oid],s:bat[:oid]) :bat[:oid]
+address CMDbat${name}signal
+comment "Return B1 $op B2 with candidates list, signal error on overflow [RDF
only]";
+pattern ${name,,}_noerror(b1:bat[:oid],b2:bat[:oid]) :bat[:oid]
+address CMDbat${name}
+comment "Return B1 $op B2, overflow causes NIL value [RDF only]";
+pattern ${name,,}_noerror(b1:bat[:oid],b2:bat[:oid],s:bat[:oid]) :bat[:oid]
+address CMDbat${name}
+comment "Return B1 $op B2 with candidates list, overflow causes NIL value [RDF
only]";
+pattern $op(b:bat[:oid],v:oid) :bat[:oid]
+address CMDbat${name}signal
+comment "Return B $op V, signal error on overflow [RDF only]";
+pattern $op(b:bat[:oid],v:oid,s:bat[:oid]) :bat[:oid]
+address CMDbat${name}signal
+comment "Return B $op V with candidates list, signal error on overflow [RDF
only]";
+pattern ${name,,}_noerror(b:bat[:oid],v:oid) :bat[:oid]
+address CMDbat${name}
+comment "Return B $op V, overflow causes NIL value [RDF only]";
+pattern ${name,,}_noerror(b:bat[:oid],v:oid,s:bat[:oid]) :bat[:oid]
+address CMDbat${name}
+comment "Return B $op V with candidates list, overflow causes NIL value [RDF
only]";
+pattern $op(v:oid,b:bat[:oid]) :bat[:oid]
+address CMDbat${name}signal
+comment "Return V $op B, signal error on overflow [RDF only]";
+pattern $op(v:oid,b:bat[:oid],s:bat[:oid]) :bat[:oid]
+address CMDbat${name}signal
+comment "Return V $op B with candidates list, signal error on overflow [RDF
only]";
+pattern ${name,,}_noerror(v:oid,b:bat[:oid]) :bat[:oid]
+address CMDbat${name}
+comment "Return V $op B, overflow causes NIL value [RDF only]";
+pattern ${name,,}_noerror(v:oid,b:bat[:oid],s:bat[:oid]) :bat[:oid]
+address CMDbat${name}
+comment "Return V $op B with candidates list, overflow causes NIL value [RDF
only]";
+
+EOF
+done
+
for func in +:ADD -:SUB \*:MUL; do
name=${func#*:}
op=${func%:*}
diff --git a/monetdb5/modules/mal/01_calc.mal b/monetdb5/modules/mal/01_calc.mal
--- a/monetdb5/modules/mal/01_calc.mal
+++ b/monetdb5/modules/mal/01_calc.mal
@@ -460,6 +460,14 @@ address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";
+pattern +(v1:oid,v2:oid) :oid
+address CMDvarADDsignal
+comment "Return V1 + V2, signal error on overflow [RDF only]";
+
+pattern -(v1:oid,v2:oid) :oid
+address CMDvarSUBsignal
+comment "Return V1 - V2, signal error on overflow [RDF only]";
+
pattern +(v1:bte,v2:bte) :bte
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
@@ -684,10 +692,6 @@ pattern add_noerror(v1:lng,v2:wrd) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";
-pattern +(v1:oid,v2:oid) :oid
-address CMDvarADDsignal
-comment "Return V1 + V2, signal error on overflow [RDF only]";
-
pattern +(v1:lng,v2:lng) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
@@ -1032,10 +1036,6 @@ pattern sub_noerror(v1:lng,v2:wrd) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";
-pattern -(v1:oid,v2:oid) :oid
-address CMDvarSUBsignal
-comment "Return V1 - V2, signal error on overflow [RDF only]";
-
pattern -(v1:lng,v2:lng) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
@@ -2813,1262 +2813,1260 @@ pattern <(v1:str,v2:str) :bit
address CMDvarLT
comment "Return V1 < V2";
+pattern <(v1:oid,v2:oid) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:bte) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:sht) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:int) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:wrd) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:lng) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:flt) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:bte,v2:dbl) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:bte) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:sht) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:int) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:wrd) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:lng) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:flt) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:sht,v2:dbl) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:bte) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:sht) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:int) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:wrd) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:lng) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:flt) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:int,v2:dbl) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:bte) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:sht) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:int) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:wrd) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:lng) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:flt) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:wrd,v2:dbl) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:bte) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:sht) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:int) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:wrd) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:lng) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:flt) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:lng,v2:dbl) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:bte) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:sht) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:int) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:wrd) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:lng) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:flt) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
+pattern <(v1:flt,v2:dbl) :bit
+address CMDvarLT
+comment "Return V1 < V2";
+
_______________________________________________
checkin-list mailing list
[email protected]
https://www.monetdb.org/mailman/listinfo/checkin-list
