Here's one to tease yourselves over. I have a board to fix and for once, I do not know how to go about it.
I designed the thing. It's battery powered, and is consuming batteries. There is a 1.0V line with nearly 40 class B fet stages, using logic level fets (Irlml6401 p-channel on top and irlml 2502 n-channel underneath) The gates are tied; That stage is pulling 10 mA on no load. It should draw basically nothing. It draws 10 mA even with the load disconnected. The 'Off' condition has -1.5V on the gates; the p channel fet sees the voltage from +1.0 to -1.5V and is fully on, and the n channel reverse biased. 'On' it is the reverse - the p channel is reverse biased, and the n channel sees +2.5V. Now the tracks are too thick to use a millivolt meter and trace where the 10mA is going. 10 mA doesn't show - I had difficulty tracing 100mA. How do I find the $*�"! current leak?? I had one thing - a fet test program which applies logic 0 to all gates and will drive one at a time high, as I press buttons. I couldn't find any gate leakage. The 5V will usually leak onto the 1.0V if a gate is gone, and I can find the fet pair that way. I will go around the fet pairs with a voltmeter and check the values, but expect to find nothing. -- Regards, Declan Moriarty. -- Author: Declan Moriarty INET: [EMAIL PROTECTED] Fat City Network Services -- 858-538-5051 http://www.fatcity.com San Diego, California -- Mailing list and web hosting services --------------------------------------------------------------------- To REMOVE yourself from this mailing list, send an E-Mail message to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in the message BODY, include a line containing: UNSUB CHIPDIR-L (or the name of mailing list you want to be removed from). You may also send the HELP command for other information (like subscribing).
