Asynchronous Logic Analyzer

[Jeremy Proffitt]

About a year ago I sent an e-mail to this group with great replys about a project - a simple asynchronous logic analyzer.  A year later, I've finally moved to a place where I can set up my lab again, and I'm back at it.   The Circuit:  I'm taking a 74x164 serial to parallel shift register and a 74x521 octal comparator.    The input for the first channel is going to the A side of the 74x521 and into the A and B inputs of the 74x164.  I'm routing Q0 of the '164 to the B input of the '521.  I then hook the = output of the '521 into the CLK of the '164.   The reasoning is that Q0 holds the last state and is being compared to the input.  When the input changes, the = output drops low, triggering '164 to clock in the next bit.  Once clocked = goes high again.   I'm having the same problems.  Random fluxuations.  The 8 outputs randomly go on and off.   What I've checked:  The Clear of the '164 is tied high.  The = input of the '521 is tied low.  All unused inputs to the '521 are tied low (that is all other 7 bits.)  And I've got bypass caps on every chip.   Any thoughts?