Hi Martin, > I have the pin-out chart for a 7473 JK flipflop and know that > at least one configuration is such that for every pulse on the Clock > the Q and ^Q outputs reverse state. What do you do with the J and K > inputs in relation to the outputs to get this configuration?
The only difference between a RS flip-flop and a JK flip-flop is that R=1=S is forbidden, but J=1=K just let toggle the flip-flop every clockpuls. The necessary connections with the outputs are made internaly by the designer. If you want not to count clockpulses, but events and you have a clock signal, connect both J and K to the event signal. If you don't have a clock, connect J and K to 1 (logic High) and connect the event signal to the clock input. All these with the assumption that logic 1 = High voltage level. Succes, Harry > > I had carefully written down the pin-out chart and failed to > write down the configuration that causes it to act as a one-stage > counter. > > I am building a chopper modulator and the complimentary > outputs are just what I need to drive the CD4016 control lines. > > Many thanks and I'll make sure it gets written down this time. > > Martin McCormick WB5AGZ Stillwater, OK > OSU Information Technology Division Network Operations Group > -- > Author: Martin McCormick -- Author: H.C. Croon INET: [EMAIL PROTECTED] Fat City Network Services -- 858-538-5051 http://www.fatcity.com San Diego, California -- Mailing list and web hosting services --------------------------------------------------------------------- To REMOVE yourself from this mailing list, send an E-Mail message to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in the message BODY, include a line containing: UNSUB CHIPDIR-L (or the name of mailing list you want to be removed from). You may also send the HELP command for other information (like subscribing).
