Quoting Miroslav Lichvar <mlich...@redhat.com>:
On Tue, Nov 29, 2016 at 09:54:36AM +0100, Miroslav Lichvar wrote:
On Mon, Nov 28, 2016 at 01:38:35PM -0600, Dan Drown wrote:
> Additional information:
> https://dan.drown.org/stm32/adev-mix.png
> ^ comparison of various adev (think "standard deviation of frequency's
> stability when sampled at the given interval")
> TCXO ADEV - TCXO vs GPS PPS, timer input compare measurement (20ns/2e-8
> resolution samples)

Do you have an adev plot from this system when the frequency
stabilization is disabled so we could see the difference?

I think I misunderstood. This is not a clock stabilized by
chronyd+tempcomp, but rather an adev of the offset between the
TCXO PPS and GPS PPS, not involving the system clock, right?

The TCXO ADEV was measured on the microcontroller itself. I setup the timer for input capture and measured the timer cycles between GPS PPS pulses. So chrony and tempcomp were not involved in that measurement. So that line shows the performance of the TCXO I selected (plus the error the limitations of my test added)

The other lines are comparing chrony controlling the system clock vs. the upstream clock source.

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