> On Jan 18, 2017, at 09:56, Miroslav Lichvar <mlich...@redhat.com> wrote:
> Avoiding the asymmetry on the PCIe bus is what I'm most interested in.

I’m not sure how much asymmetry on the PICe bus there is. Or how it affects 

PCIe asymmetry/delay  won't affect the actual timestamps. To my knowledge, the 
only asymmetry there is the PHY connection.


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