I think that Cil is correct here. It is reporting i as live because you use it
before you set it
(i+=n). If you change n=10 to n=10,i=0, Cil reports neither i nor n as live at
1. I think that this
is correct for liveness analysis.
Jesse Draper
On 10/25/2012 06:13 AM, Alex Susu wrote:
> Hello.
> I have some issues with the liveness module of CIL.
>
> I used a bit on a couple of simple C programs and the results I get are
> a bit strange.
>
> More exactly, for the program below:
> int main() {
> int n;
> int i;
>
> for (n = 10; n > 0; n--) {
> i += n;
> }
> return 0;
> }
>
> when I give:
> cilly.asm.exe --out ./app2.cil.c --doLiveness --live_func main
> --live_debug ./app2.i
>
> I get the following live variable sets for each Basic-Block (BB):
> 1: i___0(int ), Note: here we should have n(int ), as well
> 2: n(int ),i___0(int ),
> 3: n(int ),i___0(int ),
> 4:
> 5: n(int ),i___0(int ),
> 6:
> So the problem is for this program that for BB 1, we have live var set
> {i} and we
> should have {i, n}.
>
> Note that in the liveness module I added the instruction
> (Cfg.printCfgFilename
> "myfunc_cfg.dot" fd), which created the following myfunc_cfg.dot file:
> digraph CFG_main {
> 1 [label="1: instr"] Note: BB 1 is instr n = 10
> 1 -> 2
> 2 [label="2: loop"] Note: BB 2 is the while loop - not really a
> BB, IMO
> 2 -> 3
> 3 [label="3: if"] Note: BB 3 is the if n > 0
> 3 -> 5
> 3 -> 4
> 4 [label="4: break"]
> 4 -> 6
> 5 [label="5: instr"] Note: BB 5 is statements i += n; n--;
> 5 -> 2
> 6 [label="6: return"]
> }
>
> Best regards,
> Alex
>
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