I'd LOVE to see this documented in one place, as well. I did find this on the 2950's: "8 MB memory architecture shared by all ports" http://www.cisco.com/en/US/prod/collateral/switches/ps5718/ps628/product_data_sheet09186a00801cfb64.html
Nothing elsewhere... -- Stephen F. Cobb • Senior Sales Engineer CCNA/CCDA/DCNID/ATSP Telecoast Communications, LLC • Santa Barbara, CA o 877.677.1182 x272 • c 760.807.0570 • f 805.618.1610 aim/yahoo telecoaststephen On Tue, Apr 27, 2010 at 8:35 AM, Jeff Kell <[email protected]> wrote: > Does anyone have a pointer to buffer specifications for the access layer > Catalyst models (2950/2960/3550/3560)? > > Interested in per-port buffer specs (if applicable) or shared buffer > sizes by model. > > The word "buffer" interestingly enough does not appear anywhere in the > 2960 data sheets :-) > > I've heard discussions (and seen evidence) of some pretty shallow > buffering abilities on some of these switches but never seen any > concrete values. > > Jeff > _______________________________________________ > cisco-nsp mailing list [email protected] > https://puck.nether.net/mailman/listinfo/cisco-nsp > archive at http://puck.nether.net/pipermail/cisco-nsp/ > _______________________________________________ cisco-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/
