> From: Saku Ytti [mailto:[email protected]]
> Sent: Wednesday, May 18, 2016 6:06 PM
>
> On 18 May 2016 at 19:44, Adam Vitkovsky <[email protected]>
> wrote:
>
> > I'm not that familiar with these small ASICs -or actually FPGAs (as a
> crossover between ASIC and NPU).
> > But since in FPGAs not everything is programed in HW (I'm guessing),
> wouldn't the execution time be partly dependent on what features are
> enabled? So then higher clock-rate would mean that you can execute more
> instructions per given Tc. That is to be able to do more advanced stuff while
> sustaining the nominal pps rate?
> > Just thinking out loud.
>
> If I understood you right, you're saying 'maybe we were lookup starved,
> ended up buffering due to waiting for lookup engine'.
>
> But that is not microburst, microburst is egress interface being congested,
> lookup engine being congested is just box being oversubscribed with traffic.
>
Yes I somehow got locked only one sentence from your original post:
> ME3600X is what 65Mpps box, so that's pretty much only thing we need
>to know from ASIC performance POV. Having higher clock ASIC doing same
>65Mpps is completely irrelevant.
And started to think about lookup processing starvation and how it could be
alleviated by faster clocking and disregarded the 10GE to 1GE thing completely,
my bad.
You folks are right, the only option to cope with drops due to microbursts are
deeper delay bandwidth buffers.
But one has to strike the balance right as having these too deep can introduce
too much delay into the network.
At some point you want the packets to get dropped so TCP can do its thing and
adjust.
adam
Adam Vitkovsky
IP Engineer
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