> Mack McBride
> Sent: Friday, July 22, 2016 11:46 PM
>
> On the older 3550 and 3560 there were no hardware counters for ACLs.
> I am assuming that is true with the 3850 as well.
> On the ASR1006, you have a massively parallel software processor that
> handles all forwarding (the Cisco FP).
> So technically it is software but it acts more like reprogrammable hardware.
> Each FP has a large number of multi threaded cores.
> The ESP 200 has around 248 cores, which can each handle multiple (four
> each) threads.
> This means that you effectively handle 992 threads simultaneously.
> That translates to 5+ CPU cycles per bit at 64 byte packets.
> Meaning even with minimum sized packets the processors get about 2500
> cycles for each packet.
>
I don't understand the meaning of cycles per bit calculation.
Although in case of ASR1k QFPs the PPEs are getting whole packet bodies, why
should PPEs be concerned about anything else but the PPS rate and the number of
operations and mem accesses needed for a given packet, unless they are doing
DPI.
adam
Adam Vitkovsky
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