*Position: Physical Design Engineer / RTL Design Engineer* *Client : Nvidia, Bay Area.*
*Requirements:* - RTL Design, Verification, Synthesis, DFT, FPGA Prototyping, Emulation - - Physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets - - Physical design, flow automation, floorplan, power/clock distribution, chip assembly and P&R, timing closure - - Static timing analysis, power and noise analysis and back-end verification *TOTAL EXPERIENCE :* *RELEVANT EXPERIENCE :* *OFFICIAL NOTICE PERIOD :* *CURRENT RATE PER HOUR :* *VISA STATUS :* *EMAIL ID :-* *up2datec...@gmail.com <up2datec...@gmail.com>* -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to citrix-and-sap-problems+unsubscr...@googlegroups.com. To post to this group, send email to citrix-and-sap-problems@googlegroups.com. Visit this group at https://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/d/optout.