SoC designs Silicon Valley,CA
Duration- 12 months Rate Market *Job Description:* • Responsible for physical implementation and timing closure of complex SoC blocks • Define the floorplan, including pin placement, power busing, placement of blocks and macros • Design complex clocking structures • Execute place/route, signal integrity avoidance/fixing, power/clock analysis, timing closure, noise analysis and preliminary DRC/LVS *Qualifications and requirements*: • BS/MS degree in Electrical or Computer Engineering, with 4 or more years of related experience • Experience using Cadence Tools, SOC Encounter, ETS, QRC, EPS, PVS • Successful tapeout experience of multiple complex chips at 28nm, 45 nm or below • Expertise in floorplanning, physical synthesis, CTS, placement and routing • Hands on experience with STA (Primetime) and physical verification (Calibre, PVS) • Understanding of deep sub-micron design problems and solutions (leakage power, power gating, multi-Vt, signal integrity, DFM etc.) • Proficiency with Linux, Perl and Tcl Please include the below Required Details . Consultant Full Name: Email Id: Phone/Cell Number : Current Location : Visa Status: Hourly Rate on c2c/w2 all inclusive: Availability: Relocation Yes/No: Thanks, Sam Email [email protected] Phone 732-917-4895 Fax 732-875-0233 SourceChip, Inc 7 Rustic Drive, North Brunswick, NJ – 08902 Visit us www.sourcechip.net -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/groups/opt_out.
