*Hi**,* *A Systems LLC* is looking for *STA(*Static timing analysis*) Engineer** at Santa Clara, CA*
Please share your updated resume to Amit at amit@*asystemsllc.com* <http://gmail.com/> OR feel free to contact me at *404-462-0967* <404-462-0686> *Description for this role is belo**w* *:* *OPT Accepted * *Rate -$40/hr on C2C* Duration: 6 months+ Job Details · Chip level static timing analysis and timing closure · Understand design constraints, develop scripts for synthesis and formal equivalence and close pre-layout design timing · Synthesis and LEC of large gate count, high speed blocks Required Skills: · Developing constraints, Static timing analysis(STA) and timing closure at the chip level – Synopsys Primetime · Synthesis of high speed, large gate count designs using Synopsys Design Compiler, or RTL Compiler · Formal verification with tools such as Conformal, Formality or other industry standard tool · Experience on 28nm or lower node designs Good To have: · DFT implementation at the block level · CDC checking using tools such as Spyglass, 0in · Lint checking with Spyglass or other industry standard tools · Scripting in Perl/Shell and Tcl · Good Communication and Interpersonal Skills *Thanks & Regards,* *Amit * *A Systems LLC 11175 Cicero Drive, Suite 100 Alpharetta, GA 30022 Direct: 404-462-0967 | **Email:[email protected]* <email%[email protected]> -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/d/optout.
