Etienne M. Gagnon wrote: > Time 2 > Processor 2: > uses locks to read var1. This forces all "write" caches on all > processor to "flush" to memory, and the local "read" cache to be updated.
Small error. No "write cache flush" required. The write flush is done as part of synchronization "independently on each processor". Only thing required: "read cache update". My counter-example still works. Etienne -- Etienne M. Gagnon http://www.info.uqam.ca/~egagnon/ SableVM: http://www.sablevm.org/ SableCC: http://www.sablecc.org/ _______________________________________________ Classpath mailing list [EMAIL PROTECTED] http://mail.gnu.org/mailman/listinfo/classpath
