Ref: Your note of Wed, 25 Jun 2014 23:24:20 +0200 I had a look through the trace to find out what happened to the registers. Turns out it's quite simple. They are copied from the 64-bit first level register save area to a system save area near the start and restored to the DFHITS 64-bit first level register save area just before returning.
In the successful case, they are then loaded up and control is returned. In the failing case, flag SSASIMCB in the save area is non-zero (the comment in the SVCSAVE macro says "MVS/OS control blocks defined"), and this causes several thousand more instructions to be executed before returning, including calling SVC 204, which overwrites the first level save area! Looks like it's most likely to be a bug in zCMS, possibly triggered by the fact that the newer Pipelines uses the MVS ESPIE macro rather than intercepting PSWs to trap storage address problems. (Intercepting PSWs still works in zCMS anyway, as the z/VM interrupt handlers emulate the ESA interrupt process, including loading the ESA new PSW). I'll follow this up with someone in z/VM. Jonathan Scott
