> Nicolas Neuss <[EMAIL PROTECTED]> writes:
> > C (dynamic) C (static) CMUCL > > P2 (400 MHz) 4.3 sec 1.1 sec 1.5 sec > > P4 (2.4 GHz) 0.59 sec 0.30 sec 0.28 sec > > > > I would suspect that you might observe similar results. > > Unfortunately, I have to correct myself. I have redone those measurements > now, and the numbers have changed (at least for the Pentium 4). I frequently experience that due to its overly long pipeline, the P4 frequently behaves a bit "strange" in benchmarks. While having such a long pipeline is a drawback in many situations, I also have seen some rare cases where it leads to tremendous, almost incredible speed gains in LISP code when comparing to scaled-up P3 values. Anyway, coming back to the original question, there is a deeper principle underlying Ryan's considerations, and I would like to refer to e.g. http://www.cs.rice.edu/~taha/MSP/ for a starting point into multi-stage programming. -- regards, [EMAIL PROTECTED] (o_ Thomas Fischbacher - http://www.cip.physik.uni-muenchen.de/~tf //\ (lambda (n) ((lambda (p q r) (p p q r)) (lambda (g x y) V_/_ (if (= x 0) y (g g (- x 1) (* x y)))) n 1)) (Debian GNU)
