On Jul 4, 2012, at 10:41 PM, Nathan Day wrote:

> It must if 64bits is read in that mean you have just read in two 32bit words. 
> So to put a 32bit word in a 64bit register some bit must be ditched, in some 
> way, and if the CPU is optimise to only work with 64bit word alignment (don't 
> know how intel does it), then to get 32 bit aligned words it must do some bit 
> shift.

Yes, but this happens in hardware way, way down inside the ALU, where I 
seriously doubt it takes any extra time at all. (It's not a 'shift' at that 
level so much as the way address lines are wired up to each other.) You'd have 
to consult the gory details of the timing diagrams in Intel's detailed 
instruction-set manuals to find out. In any case it has nothing to do with the 
current discussion.

The CPU cache is a lot like virtual memory, just lower level. The 'page size' 
is called a 'cache line' and it's smaller, maybe 64 or 128 bytes. When the CPU 
needs to access an address it first looks in the cache to see if a cache line 
containing that address is available; if so it reads it directly from there 
(which is extremely fast since it's on-chip), otherwise it has to wait to load 
the entire cache line from RAM, then fetch the address.

The cache _only_ deals in blocks of 128/256/whatever bytes, just like the disk 
controller only reads/writes entire sectors. It can't manage 4-byte or 8-byte 
values any more than the disk controller can. It has no idea whether the CPU 
wants a byte or a 32-bit word or a 64-bit one, it just knows how to read and 
write pages from off-chip RAM.

http://en.wikipedia.org/wiki/Cache_line

And the real point in this discussion: Just like with VM but on a smaller 
scale, the better your working set of data fits into the CPU cache, the faster 
your code will run. And the cache will, obviously, hold twice as many int32_t's 
as it will NSIntegers (in 64-bit mode.) So using smaller int sizes _can_ 
improve performance.

—Jens
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