OSU EECS will be hosting a colloquium today at 11am, and one tomorrow at 9am, both in Owen 106.
Monday March 7 11:00 - 11:50 AM Owen 106 Behnam Analui Ph.D. Candidate Electrical Engineering Caltech Integrated Systems for High-Speed Wireline Communication Wireline communication at 10Gb/s and beyond faces serious challenges. Channel impairments such as attenuation of electrical transmission line at high frequency and modal dispersion of multi-mode optical fiber degrade received signal quality significantly and result in bit error rates as large as 10-2. Adaptive equalization is a practical technique for reducing the channel response impacts and for enabling higher data rates and longer transmission distances. In the first part of the talk, the impact of jitter on link reliability is discussed. An analytical treatment of data dependent jitter that has resulted in design insights for jitter minimization will be presented. The study provides basic theoretical understanding of previously measurement-based roots of data dependent jitter distribution. It also enables prediction of jitter impacts of general LTI systems. Experimental data verify accuracy of predictions for various components and demonstrate less than 7.5% error. In the second part, a new approach for adaptive equalization is introduced. An eye-opening monitor architecture is presented that leverages high-speed integrated analog signal processing to evaluate the quality of the received signal. It generates a two-dimensional error map, which is directly correlated to the eye diagram shape. The evaluation result can be used as a cost function for the coefficient optimization algorithm of the equalizer. Measurements of an integrated CMOS prototype demonstrate up to 68dB error dynamic range at 10Gb/s input rate. Tuesday March 8 9:00 - 9:50 AM Owen 106 Hamid Mahmoodi Ph.D. candidate Electrical and Computer Engineering Purdue University Circuit Design in Nano-Scale Technologies: SRAM Perspective To achieve higher integration density and performance, silicon technology has been aggressively scaled for more than 40 years. As silicon devices are scaled down to sub-100nm regimes, power dissipation and process variations are becoming major challenges for circuit design. For continued scaling of technology, these issues must be addressed at all levels of abstraction. The inter-die process variations, coupled with the intra-die variations can result in significant delay spread in logic circuits and even functional failures in SRAM cells. This talk will primarily focus on statistical design methodologies for yield enhancement in SRAM. A statistical modeling approach will be developed to model failure probability of an SRAM cell and the yield of an SRAM array. Based on the developed models, a methodology to statistically design the SRAM cell and the memory organization will be presented. The developed methodology can be used at an early stage of a design cycle to enhance memory yield in nano-meter regimes. The proposed design approach provides, for the first time, an integrated device, circuit, and architectural level statistical optimization strategy for SRAM. In addition to the statistical design, an adaptive body biasing technique will be presented to further improve the yield of SRAM. The last part of the talk will discuss the speaker's research vision and future research directions. Biography Hamid Mahmoodi received the B.S. degree in electrical engineering from Iran University of Science and Technology, Tehran, Iran, in 1998 and the M.S. degree in electrical and computer engineering from the University of Tehran, Iran, in 2000. He is a PhD candidate in electrical and computer engineering at Purdue University, West Lafayette, IN. His research interests include low-power, robust, and high-performance circuit design for nano-scale bulk CMOS and SOI technologies. He has more than 35 refereed publications in journals and conferences. He was a recipient of the Best Paper Award of the 2004 International Conference on Computer Design. _______________________________________________ Colloquium mailing list [email protected] https://secure.engr.oregonstate.edu/mailman/listinfo/colloquium
