After today's colloquium, our next will be this Friday at 11:30, still scheduled for Covell Hall 216. For more colloquium listings, please see http://eecs.oregonstate.edu/graduate/colloquium/.
Friday April 1 11:30 - 12:20 PM Covell 216 Janusz Rajski Chief Scientist Design Verification and Test Division Mentor Graphics Design for Manufacturing and Manufacturing for Design: Closing the Loop Sub-wavelength lithography processes are introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to offset "cosmetic" improvements in tools and methodologies. If EDA companies are to assist the semiconductor industry at the 90nm and 65nm nodes and below, there must be profound changes to existing tools and new flows have to be established. In particular, there is a need for new technologies that allow designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout and test process. One of the most fundamental changes is the integration of DFM and DFT flows, especially in closing the loop between manufacturing and design. DFM-oriented test uses DFM rules, recommendations, and guidelines to optimize test quality. Analysis of test data from manufacturing test creates a true goldmine of information for calibrating today's largely qualitative DFM rules and computing yield sensitivity functions. Biography Janusz Rajski holds Ph.D. degree from the Poznan University of Technology, Poland. He is a Chief Scientist and Director of DFT Engineering at Mentor Graphics Corporation. He has published over 100 technical papers and holds seventeen US and international patents in the area of design for test. He is also the principal inventor of Embedded Deterministic Test (EDT(tm)) technology and chief architect of the first commercial test compression product TestKompress(tm). Janusz received a number of awards including the 1993 Best Paper Award for a paper on logic synthesis published in IEEE Transactions on CAD, VTS 1995 and 1998 Best Paper Awards for papers on embedded test, and ITC 1999 and 2004 Honorable Mention Awards for papers on Logic BIST and Embedded Deterministic Test. In 2003 the President of Poland awarded the title of Professor of Sciences to Janusz for his fundamental contributions in the area of design and test of digital circuits and systems. _______________________________________________ Colloquium mailing list [email protected] https://secure.engr.oregonstate.edu/mailman/listinfo/colloquium
