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Seminar: ECE Faculty Candidate Tuesday February 14th 10:00am-10:50am KEC 1007 (Seminar Room) Patrick Yin Chiang PhD. Candidate Abstract: Precision Clock Synthesis for High
Speed Serial Link Transceivers New developments in high
speed CMOS serial links have been crucial in matching off-chip system bandwidth
with the ever increasing on-chip demand. As transistor scaling pushes
data rates higher, improving the timing precision in transceiver architectures
becomes a key factor in the performance of future high speed serial links. Conventional serial links
architectures typically use multi-phase clocking structures to achieve a pin
bandwidth faster than the on-die logic switching speed. However,
multi-phase clocking architectures suffer from significant sources of timing
uncertainty, namely power supply induced jitter and static phase offset resulting
from process mismatch. These jitter sources are expected to worsen in
future CMOS technologies, reducing the effectiveness of such multi-phase
transceiver architectures for very high data rates. In this talk, I will
present a new serial link architecture which addresses the timing uncertainties
caused by power supply noise and process mismatch. In contrast with multi-phase
architectures, the complementary phases of an integrated LC-VCO directly drive
the final output multiplexer in the transmitter, resonating the load and
eliminating clock buffers, thereby reducing power dissipation, power supply
induced jitter, and static phase offset. In the receiver, a similar
technique is applied, where the front-end input sampler is directly driven by a
different LC-VCO. The resulting power supply susceptibility is reduced by 10x
and process mismatch phase error by 5x. Two test chips have been designed and
fabricated in 0.13um CMOS technology, exhibiting a 20Gb/s data rate with low
power/area. The architecture, circuit design, measured results, and
future work will be presented. Biography
Patrick Chiang received the B.S. degree in electrical engineering and computer
sciences from the
In 1998, he was with Datapath Systems (now LSI Logic), working on analog
front-ends for DSL chipsets. In 2000, while collaborating with UCSD, he
implemented one of the first monolithic implementations of a complete chaotic
transceiver on a CMOS die. In 2001, he worked with Dr. Ed Lee on two
prototypes of 0.25um, 4Gb/s low power/area CMOS serial links. Recently,
his doctoral work has been on the design of precision clock synthesis
architectures for high speed serial links, resulting in the implementation of
two 0.13um, 20Gb/s low power/area CMOS serial links. In 2004, he consulted
at Telegent Systems, |
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