Seminar: ECE Faculty Candidate Wednesday February 22nd 11:00am - 11:50am Kelley 1005
Pavan Kumar Hanumolu PhD. Candidate School of EECS Oregon State University Performance Enhancement Techniques for Signaling Systems In order for the aggressive scaling of transistors to truly benefit the performance of large and complex digital systems, the communication bandwidth between ICs must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major bottleneck in overall system performance. In addition, supply voltage scaling, increasing device leakage, and increased noise make existing signaling circuits inefficient and difficult to scale. This talk will present both analog and digital enhancement techniques to mitigate scaling related issues and improve the performance of building blocks used in high-speed signaling systems. A hybrid analog/digital clock and data recovery (CDR) architecture that improves the tracking range of traditional CDRs by an order of magnitude will be presented. This CDR also employs an improved analog phase-locked loop architecture to circumvent fundamental scaling problems such as low voltages and reduced output impedances. An all-digital CDR architecture that obviates the need for any analog components while achieving error-free operation will be discussed. Several digital signal processing techniques used to achieve this performance will be presented. Finally, a digital-to-phase converter(DPC) with a resolution that exceeds the state-of-the-art DPC resolution by an order of magnitude will be reported. The proposed DPC achieves better than 100 femto-second resolution. Measurement results obtained from prototype chips that validate the proposed design techniques will be summarized. Bio. Pavan Kumar Hanumolu received the B.E. (Hons.) degree in electrical and electronics engineering and the M.Sc. (Hons.) degree in Mathematics from the Birla Institute of Technology and Science, Pilani, India, in 1998, and the M.S. degree in electrical and computer engineering from the Worcester Polytechnic Institute, Worcester, MA, in 2001. He is currently working toward the Ph.D. degree in electrical engineering at the Oregon State University, Corvallis. Mr. Hanumolu received Analog Devices Outstanding student designer award in 2002 and the Intel Ph.D. fellowship in 2004. He worked at Cypress Semiconductors and Intel research labs on various analog-mixed signal circuits. _______________________________________________ Colloquium mailing list [email protected] https://secure.engr.oregonstate.edu/mailman/listinfo/colloquium
