Monday October 2 4:00 - 4:50pm Kelley 1001
Patrick Chiang, Ph.D. Assistant Professor School of EECS Oregon State University Using Moore's Law to Extend Moore's Law One of the most common electrical engineering viewpoints in the 21st century has been the eventual end to transistor scaling (Moore's Law) due to fundamental physical limitations. Much current research focus has recently touted the new age of nanotechnology, such as quantum computing, magnetics/spintronics, and MEMS. While these research areas certainly hold enormous potential, such technologies will succeed only if they are integrated together with the semiconductor processing goliath and its vast amount of computational ability-thereby taking full advantage of nanoelectronics promise. At the same time in parallel, Moore's Law will continue to scale transistors, giving us unprecedented computing performance/benefits that we unknowingly take for granted. In this talk, I will describe in broad context how we can use the benefits of transistor scaling to effectively enhance the longevity and usefulness of such transistor scaling. I will first talk about my past and current research in designing new circuit architectures in deep submicron technologies that take advantage of CMOS's benefits, namely ubiquitous transistors, increased transistor performance, and system-on-a-chip possibilities--while compensating for its growing disadvantages, such as process variation, inaccurate parasitic/device modeling, and increased design time/cost. I will then discuss how such research in CMOS circuits provides a natural interface with non-CMOS technologies, creating new and interesting interdisciplinary research areas. Curiosity, an open mind, and contrarian thought are especially welcome. Biography: Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2006. In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications (now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. His interests are in the design and implementation of new architectures for mixed signal circuits in deep submicron CMOS. In high speed serial links, his interests include the design of low power, high data rate, parallel I/O's; and the implementation of 20+ GHz, 4-5 bit low power ADCs for limited bandwidth channels. In RF circuits, his research revolves around the design of reconfigurable, self-healing RF transceivers to compensate for process variation in future CMOS technologies. _______________________________________________ Colloquium mailing list [email protected] https://secure.engr.oregonstate.edu/mailman/listinfo/colloquium
