Thursday ***Special time, date, and location*** May 3 11:00 - 12:20 PM Kelley 1003
Frank O'Mahony Senior Research Scientist Circuit Research Lab Intel "Advanced Analysis, Design, and Measurement Techniques for Multi-Gb/s Data Links" Data rates for state-of-the-art chip-to-chip data links across copper interconnects is today in the range of 10-20Gb/s. Increasing aggregate link data rates enables performance improvements in computing platforms, which today can include multiple processors, high-bandwidth memory, graphics processors, and other peripherals. In addition to data rate, however, a balanced link design must also consider the power efficiency, variation tolerance, noise immunity and self-test capabilities required for high-volume and low-power systems. This talk will discuss how links are designed today to take all of these factors into account and cover specific examples of behavioral link modeling, circuit design, and test and measurement for a 20Gb/s data link prototype. Biography: Frank O'Mahony received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1997, 2000, and 2003, respectively. His doctoral research focused on resonant clock distribution techniques for high-performance microprocessors. In 2003 he joined Intel's Circuit Research Lab in Hillsboro, OR where he is currently a Senior Research Scientist. His research interests include high-speed and low-power data links, clock generation and distribution, and design techniques for low-noise, variation-tolerant clocking and signaling circuits. He received the 2003 Jack Kilby Award for Outstanding Student Paper at ISSCC.
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