ECE Faculty Candidate Colloquium
Friday **Special Time and Location** February 29 11:00 - 11:50 AM Kelley 1007 Ege Engin EECS Colloquium: ECE Faculty Candidate School of Electrical and Computer Engineering Packaging Research Center at Georgia Tech High-Speed Design with Interconnects and Packages The multiple GHz clock speeds of a microprocessor's internal logic typically cannot be maintained for its off-chip signals. The main bottleneck causing this IC vs. packaging performance gap is the electrical properties of interconnects and packages. They behave as distributed circuits, causing reflections, attenuation, dispersion, and crosstalk. Moreover, high-speed digital signals are affected by power supply noise, and cause increased electromagnetic interference due to discontinuities in the transmission-line reference planes. Electromagnetic analysis of interconnects and packages has become a key element of high-speed design process to evaluate the electrical issues and optimize the existing designs. However, the complexity of the structures prohibits a full-wave analysis, which can fortunately be avoided using physics-based decomposition techniques for most purposes. In this talk, I will present new simulation methodologies that can accurately handle the analysis of a full IC package. Any simulation can only be as accurate as the input parameters provided by the user. I'll also introduce a new method for characterization of the dielectric constant and loss tangent of dielectrics. In the light of these new technologies and fast analysis methods, high-speed design, however, still remains to be a challenge. Revolutionary ideas are necessary to eliminate the IC vs. packaging performance gap. Biography: Ege Engin is currently Research Engineer in the School of Electrical and Computer Engineering and Assistant Director of Research at the Packaging Research Center at Georgia Tech. Prior to joining Georgia Tech, he was a Research Engineer with the Fraunhofer-Institute for Reliability and Microintegration in Berlin working on high-speed package modeling and characterization in Europe-wide research projects. He is a co-author of the book "Power Integrity Modeling and Design for Semiconductors and Systems," published by Prentice Hall in December 2007. He has more than 50 refereed publications, 4 patent applications, and has presented tutorials in international conferences in the area of high-speed design. He received his B.S. degree in electrical engineering from the Middle East Technical University, Ankara, Turkey and his Ph.D. with Summa Cum Laude from the University of Hannover, Germany in 2004.
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