Monday April 21 4:00 - 4:50 PM Kelley 1001
Patrick Chiang Assistant Professor School of Electrical Engineering & Computer Science Oregon State University Oregon State VLSI Research Group Overview The VLSI Research Group at Oregon State University, started 1.5 years ago, is pursuing several interesting projects at the intersection of computer architecture, digital/analog circuit design, devices, and communications. In this talk, I will describe at a high level some of the projects and collaborations underway in our group. Specifically: 1) P3 (Power, Process, Parallelism); 2) NOCHI (Networks-on-a-Chip Using Heterogeneous Interconnect); 3) Ultrawideband RF for Short-Range Interconnect (with Professor Liu); 4) 10+ GSs, Low-Power ADCs; 5) international collaborations with Chinese institutions. As much of this research is still a work in progress, undergrads/grads/professors are welcome to come participate and hopefully ask some tough questions. Biography: Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007. He is currently an assistant professor of electrical and computer engineering at Oregon State University. In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications(now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In Summer 2007, he was a visiting professor at the Institute of Computing Technology, Chinese Academy of Sciences, where he collaborated on the design of multi-gigahertz ADCs and high speed serial links. His interests are in the design and implementation of new architectures for mixed signal circuits in deep submicron CMOS, focusing specifically on low power consumption and process compensation techniques.
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