Monday March 9 4:00 - 4:50 PM Kelley 1001
Scott Fairbanks Post-Doctoral Researcher School of EECS Oregon State University The Lackey self-timed switch-fabric design framework This talk introduces a design framework for self-timed communication networks where simplicity is the primary design motivator. This talk demonstrates how to rapidly build useful, and high performance self-timed or elastic communication networks. The networks are extensible to include an arbitrary number of Producers and Consumers. Each switch within the network is built from multiple instances of a Latch Control Element (LaCkEy). The Lackey is a general circuit for self-timed data control. It is built once and then configured to implement a wide range of data routing functions. The circuits presented in this paper seek to maintain high performance, at a minimal cost in complexity. The complexity of a self-timed switch network is considered at three levels of abstraction: the gate, the switch, and the network. At each level of abstraction complexity is considered and minimized. Unique circuits are eschewed for configurable ones. Circuitry is organized into an escalating hierarchy of repeatable parts. Biography: Scott Fairbanks obtained his BSEE from UCSB in 1995 and his PhD from Cambridge University in 2005. His thesis investigated ways to generate high precision timing signals on a VLSI chip using self-timed circuits. He worked for thirteen years at the labs of Sun Microsystems. There he contributed to a project that sought to scrap the global clock in a Sparc processor and replace it with self-timed data control circuits. He also co-led a project that investigated using his Distributed Clock Generator for future Sun microprocessors.
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