28-56Gb/s Standards and Design Implications is coming at 10/17/2016 - 4:00pm

DEAR 118
Mon, 10/17/2016 - 4:00pm

Frank O'Mahony
Principal Engineer, Intel

Over the past decade, wireline data rates have doubled about every four years
to keep pace with aggregate system bandwidth requirements. Electrical
signaling standards for networking, telecom and storage applications –
including Ethernet and OIF-CEI – tend to be the first to define the path to
increase line rates. Today, links up to 28Gb/s/lane are being widely
deployed. Meanwhile, standards for 50-56Gb/s are being defined, and we are
seeing early demonstrations of transceivers and components meeting this
bandwidth. This presentation will provide an overview of standards, circuit
architectures and design tradeoffs for 28-56Gb/s links. It will start by
providing a summary of recent data rate scaling trends and standards for
28-56Gb/s and show where wireline is used in high-performance systems. Next
it will describe the key tradeoffs for increasing aggregate bandwidth,
including power, channel quality and process technology capability. Then it
will discuss how recent standards have balanced these tradeoffs, and describe
the implications for circuit architecture and design, including equalization,
clocking, modulation and error correction. Finally we will summarize the
existing design data points from industry and academic publications for


Read more:

Colloquium mailing list

Reply via email to