Enabling the Next Generation of Energy-Efficient Serial Links is coming at 04/10/2017 - 4:00pm
LPSC 125 Mon, 04/10/2017 - 4:00pm Tawfiq Musah research scientist, PHY Research Lab, Intel Corporation, OR Abstract: As bandwidth demand for off-chip interconnect continues to increase, optimizing I/O energy efficiency is essential for computing platforms ranging from handheld devices to high-end data centers. Many server and desktop platforms contain conventional board and packaging topologies that have been used for decades. Complex equalizers are therefore required to signal across these channels at high rates. This has resulted in steep trade-offs between scaling I/O rates and maintaining high energy-efficiency. This presentation will highlight design challenges to scaling multi-Gb/s I/O beyond 10Gb/s, and use a data-rate scalable bidirectional link design to showcase circuit and system techniques to overcome these challenges. The role of ADC/DSP-based I/O design approach in enabling the next generation of energy-efficient links will also be discussed. Bio: [node:field-speaker-bio:text] Read more: http://eecs.oregonstate.edu/colloquium/enabling-next-generation-energy-e... [1] [1] http://eecs.oregonstate.edu/colloquium/enabling-next-generation-energy-efficient-serial-links
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