Breaking Data Silos: IC Design, Manufacturing Test, System Quality & Reliability is coming at 01/06/2020 - 4:00pm
Linus Pauling Science Center 125 Mon, 01/06/2020 - 4:00pm Anne Meixner Founder, The Engineers’ Daughter LLC Abstract: When an engineer observes a new solution there exists a natural resistance to even considering adoption. Sometimes the industry is not quite ready for it, sometimes it’s a matter of finding your engineering customer. Such has been my experience with IP manufacturability. An observation I made in 2008 regarding IC test data reporting at Intel has evolved over a 12-year period. From reporting out IP failure rates for any System On Chip (SoC) I have focused the concept into solving the business barriers to breaking the data silos for a specific industry sector. In this presentation I share what sparked the observation. From the DATA1 2016 Workshop paper entitled Improved Understanding of IP Manufacturability—A Proposal to Share Data between Fab, Test and Design, I explain the initial concept and summarize the Intel proof of concept. Learnings from the past 3 years have homed in on the barriers to sharing data across the range of design, manufacturing and system integrator entities. This has resulted in focusing on the automotive electronics industry sector. Evolving this idea required working with a diverse engineering team at Intel. Once I left Intel it required seeking out feedback from engineers and engineering executives to determine the real barriers. The paragraphs below describe the data silo problem and the approach to a solution. System on a Chip (SoC) design methodology results in a rapid design of IC products due to usage of Intellectual Property (IP) blocks. Understanding IP contributions has distinct benefits in enhancing System on a Chip (SoC) yield, quality and reliability. Successful IP learning requires IP design data. Yet the semiconductor industry has knowledge siloed into Design, Fab and Test which inhibit a correspondingly rapid learning for yield, quality and reliability of ICs. Both Integrated Device Manufacturers (IDMs) and the Foundry eco-system continue to suffer from lack of connections between these silos. This presentation proposes data structures specific to IP design characteristics for test manufacturing data system that can connect these silos. Business barriers exist to connecting the knowledge siloed into Design, Fab and Test areas. In the Foundry eco-system these barriers become thicker. Setting up a data exchange that guarantees security and payment could facilitate sharing IP knowledge. 1 Defects, Adaptive Test, Yield and Data analysis Workshop Bio: Read more: https://eecs.oregonstate.edu/colloquium/breaking-data-silos-ic-design-ma... [1] [1] https://eecs.oregonstate.edu/colloquium/breaking-data-silos-ic-design-manufacturing-test-system-quality-reliability
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