Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2025-06-30 13:05:07 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new.7067 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Mon Jun 30 13:05:07 2025 rev:24 rq:1288946 version:20250513 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2025-04-07 19:15:17.564641429 +0200 +++ /work/SRC/openSUSE:Factory/.cpuid.new.7067/cpuid.changes 2025-06-30 13:06:37.850264786 +0200 @@ -1,0 +2,9 @@ +Thu Jun 5 19:32:38 UTC 2025 - Jan Engelhardt <[email protected]> + +- Update to release 20250513 + * DB updates for Intel Alder Lake, Arrow Lake, Twin Lake, Panther + Lake, Bartlett Lake, Raptor Cove, Wildcat Lake, Xeon 6 Granite + Rapids & Sierra Forest; for Hygon; and for AMD Shimada Peak. + * Added MS Hypervisor details, 256BITSGX, EGETKEY256, EREPORT2. + +------------------------------------------------------------------- Old: ---- cpuid-20250316.src.tar.gz New: ---- cpuid-20250513.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.GfAQNy/_old 2025-06-30 13:06:38.906308541 +0200 +++ /var/tmp/diff_new_pack.GfAQNy/_new 2025-06-30 13:06:38.906308541 +0200 @@ -1,7 +1,7 @@ # # spec file for package cpuid # -# Copyright (c) 2024 SUSE LLC +# Copyright (c) 2025 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: cpuid -Version: 20250316 +Version: 20250513 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later ++++++ _scmsync.obsinfo ++++++ --- /var/tmp/diff_new_pack.GfAQNy/_old 2025-06-30 13:06:38.938309867 +0200 +++ /var/tmp/diff_new_pack.GfAQNy/_new 2025-06-30 13:06:38.938309867 +0200 @@ -1,5 +1,5 @@ -mtime: 1744037800 -commit: c3cd94a99c7633f51e29e67290bd8de0d90c06eee9fd01d0db7ba3f79e59a7bc +mtime: 1749152225 +commit: 263afc192bff0c81021f009aba564e0851bf3405a55ae62ea6d7807eadedacc6 url: https://src.opensuse.org/jengelh/cpuid revision: master ++++++ build.specials.obscpio ++++++ ++++++ cpuid-20250316.src.tar.gz -> cpuid-20250513.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250316/ChangeLog new/cpuid-20250513/ChangeLog --- old/cpuid-20250316/ChangeLog 2025-03-17 03:35:38.000000000 +0100 +++ new/cpuid-20250513/ChangeLog 2025-05-13 13:20:58.000000000 +0200 @@ -1,3 +1,68 @@ +Tue May 13 2025 Todd Allen <[email protected]> + * Made new release. + +Tue May 13 2025 Todd Allen <[email protected]> + * cpuid.c: Updated (0,6),(10,13),1 (Granite Rapids) with stepping names + B0/H0, from ILPMDF*. + +Mon May 12 2025 Todd Allen <[email protected]> + * cpuid.c: Corrected synth decoding (0,6),(11,7) typos: 11 was 10. + * cpuid.c: Updated synth decoding for (0,6),(10,13) Xeon 6 6x00 Granite + Rapids. + * cpuid.c: Updated synth decoding for (0,6),(10,14) Xeon 6 6x00P Granite + Rapids. + * cpuid.c: Simplified synth decoding for (0,6),(10,15) Xeon 6 6700E + Sierra Forest. + * cpuid.man: Added AMD docs: 58251, 58730. + * cpuid.man: Added new Intel docs: 820922, 835486, 843306. + +Fri Apr 25 2025 Todd Allen <[email protected]> + * cpuid.c: Changed synth decoding for (0,6),(11,5),0 stepping from + Arrow Lake-U A1 to A0, per a new spec update, 834774-007. + +Thu Apr 24 2025 Todd Allen <[email protected]> + * cpuid.c: Changed synth decoding for (11,15),(0,8) to Shimada Peak, + based on knowledge that the Zen 5 Threadripper is Shimada Peak, and + https://docs.amd.com/v/u/en-US/dh300-amd-ryzen-threadripper-tr5. + +Mon Apr 21 2025 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for (0,6),(13,5) Wildcat Lake, based on + Coreboot*. For uarch decoding, just added comments, because it's all + pure speculation. + * cpuid.c: Added comments about Hygon (9,15),(0,4) and (9,15),(0,6), for + which no core names are known. + +Sat Apr 19 2025 Todd Allen <[email protected]> + * Made new release. + +Sat Apr 19 2025 Todd Allen <[email protected]> + * cpuid.c: Added uarch & synth decoding for (0,6),(13,7) Raptor Cove, + Bartlett Lake, based on LX*. + +Thu Apr 3 2025 Todd Allen <[email protected]> + * cpuid.c: Added 7/1/ecx asymmetric RDT-[AM]. + * cpuid.c: Added 0x12/0/eax 256BITSGX EGETKEY256 & EREPORT2. + * cpuid.c: Changed leaf 0x1e subleaf walk to use to 0x1e/0/eax as + max_subs, per new documentation. + * cpuid.c: Added 0x27 leaf. + * cpuid.c: Added 0x28 leaf. + +Mon Mar 31 2025 Todd Allen <[email protected]> + * cpuid.c: For synth decoding for (0,6),(11,14), stop special-casing the + Alder Lake-N/Twin Lake CPUS based on "Core" brand. It's a distinction + without a difference, and the branding is too inconsistent. + +Wed Mar 26 2025 Todd Allen <[email protected]> + * cpuid.c: Corrected typo in 0x8000000a/edx: idle HLT intercept. + * cpuid.c: Added hypervisor+3/ecx (Microsoft) fields, based on LX* + patches from Nuno Das Neves: dispatch intr injection available, + GHCB root mapping available. I could find no actual docs. + +Tue Mar 25 2025 Todd Allen <[email protected]> + * cpuid.c: Comment updates about Panther Lake. Nothing substantive. + * cpuid.c: Comment updates about leaf 0x1a native model ID's. Not + conclusive or substantive. + Sun Mar 16 2025 Todd Allen <[email protected]> * Made new release. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250316/FAMILY.NOTES new/cpuid-20250513/FAMILY.NOTES --- old/cpuid-20250316/FAMILY.NOTES 2025-03-13 15:16:49.000000000 +0100 +++ new/cpuid-20250513/FAMILY.NOTES 2025-05-12 14:05:43.000000000 +0200 @@ -61,9 +61,10 @@ 2024 Core Ultra 200 Lion Cove new architecture (Arrow Lake (TSMC N3) desktop) LGA 1851 2024 " " " (Lunar Lake (TSMC N3B) AI/low power) BGA 2833 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - ? Raptor Cove? (Bartlett Lake?) (Q1'25?) LGA 1700? + ? Raptor Cove (Bartlett Lake?) (Q2'25?) LGA 1700? ? Core Ultra 300? Lion Cove refresh of Lion Cove (Arrow Lake? (Intel 20A)) (2025) LGA 1851? ? Cougar Cove? (Panther Lake (Intel 18A?)) (mobile-only?) (2025) LGA 1851? + ? Cougar Cove? (Wildcat Lake (Intel 18A?)) ? - Panther Cove? <-?-> 7th Diamond Rapids (2025) Mountain Stream LGA 9324? ? Core Ultra 400? Coyote Cove? (Nova Lake? (Intel 18A?)) (2026) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -89,19 +90,20 @@ Hybrids: Launch Combined P-cores E-cores - --------------------------------------------------------------------- - 2020 Lakefield 1x Sunny Cove + 4x Tremont (more of a prototype) - --------------------------------------------------------------------- + ---------------------------------------------------------------------------- + 2020 Lakefield 1x Sunny Cove + 4x Tremont (more of a prototype) + ---------------------------------------------------------------------------- 2021 Alder Lake {2,6,8}x Golden Cove + {0,8}x Gracemont 2022 Raptor Lake 8x Raptor Cove + 16x Gracemont + ---------------------------------------------------------------------------- 2023 Meteor Lake {2,4,6}x Redwood Cove + {4,8}x Crestmont - --------------------------------------------------------------------- - 2024 Arrow Lake {6,8}x Lion Cove + {8,12,16}x Skymont (desktop) - 2024 Lunar Lake 4x Lion Cove + 4x Skymont (AI/low power) - --------------------------------------------------------------------- - ? Panther Lake Cougar Cove? + Darkmont + ---------------------------------------------------------------------------- + 2024 Arrow Lake {6,8}x Lion Cove + {8,12,16}x Skymont (desktop) + 2024 Lunar Lake 4x Lion Cove + 4x Skymont (AI/low power: niche, one-off) + ---------------------------------------------------------------------------- + ? Panther Lake Cougar Cove? + Darkmont? (old speculation is Darkmont, news articles say Skymont, LX* says Crestmont(!)) ? Nova Lake Coyote Cove? + Arctic Wolf? - --------------------------------------------------------------------- + ---------------------------------------------------------------------------- Intel Atom architectures: @@ -257,7 +259,7 @@ Excavator Carrizo Carrizo Toronto Brown Falcon/Merlin Falcon (+) Bristol Ridge/Stoney Ridge Bristol Ridge/Stoney Ridge Prairie Falcon --------------------------------------------------------------------------------------------------------------------------------------- - Jaguar Kabini/(PS4)/(Xbox One) Kabini/Temash Kyoto Kabini + Jaguar Kabini/(PS4)/(Xbox One) Kabini/Temash Kyoto Kabini NOTE: derived from Bobcat Puma (2014) Beema/Mullins Steppe Eagle (SoC)/Crowned Eagle (CPU) --------------------------------------------------------------------------------------------------------------------------------------- @@ -269,35 +271,39 @@ Desktop Desktop Enthusiast Mobile Server Embedded -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Zen (14nm) 1000: Summit Ridge 1000: Whitehaven 2000: Raven Ridge 1st Gen: Naples/Snowy Owl V1000: Great Horned Owl/R1000: Banded Kestrel + Zen (14nm) 1000: Summit Ridge 1000: Whitehaven 2000: Raven Ridge 1st Gen: 7cp1: Naples V1000: Great Horned Owl/R1000: Banded Kestrel + 1st Gen: 3cp1: Snowy Owl 1000: Dali 1000: Dali Zen+ (12nm) 2000: Pinnacle Ridge 2000: Colfax 3000: Picasso 3000: Picasso - Zen 2 (7nm) 3000: Castle Peak 2nd Gen: Rome==Starship V2000: Grey Hawk + Zen 2 (7nm) 3000: Castle Peak 2nd Gen: 7cp2: Rome==Starship V2000: Grey Hawk (update) 3000: Matisse 4000: Renoir 5000: Lucienne 7000: Mendocino Cardinal (PS5) Van Gogh (Steam Deck) ProjectX (Xbox X) Mero (MagicLeap Demophon) - Zen 3 (7nm) 5000: Vermeer 5000: Chagall==Genesis Peak 5000: Cezanne/Barcelo 3rd Gen: Milan + Zen 3 (7nm) 5000: Vermeer 5000: Chagall==Genesis Peak 5000: Cezanne/Barcelo 3rd Gen: 7cp3: Milan 6000/7000: Rembrandt V3000: still Rembrandt? Trento (Frontier super) Badami (?) - Zen 4 (5nm) 7000: Raphael 7000: Storm Peak 7000/8000: Phoenix 4th Gen: Genoa{==Stones?}(standard) - 7000: Dragon Range + Zen 4 (5nm) 7000: Raphael 7000: Storm Peak 7000/8000: Phoenix 4th Gen: 9cp4: Genoa{==Stones?}(standard) + 4th Gen: 4cp4: Raphael + 7000: Dragon Range (MI300 super) 8000: Hawk Point - Zen 4c (N5) 4th Gen: 97x4: Bergamo{==Stones-dense?}(cloud) - 4th Gen: 8xy4: Siena{==Stones-dense?}(edge) - Zen 5 (N4P) 9000: Granite Ridge AI 300: Strix Point 5th Gen: 9xy5: Turin{==Breithorn} - Zen 5c (N3) 5th Gen: 9xy5: Sorano{==Breithorn-dense}(edge?) + Zen 4c (N5) 4th Gen: 97p4: Bergamo{==Stones-dense?}(cloud) + 4th Gen: 8cp4: Siena{==Stones-dense?}(edge) + Zen 5 (N4P) 9000: Granite Ridge AI 300: Strix Point 5th Gen: 9cp5: Turin{==Breithorn} + Zen 5c (N3) 5th Gen: 9cp5: Sorano{==Breithorn-dense}(cloud?) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - ? 9000: Shimada Peak? 9000: Fire Range + ? 9000: Shimada Peak? 9000: Fire Range 5th Gen: 4cp5: Grado? ? 9000: Krackan Point(edge)? ? AI ???: Strix Halo==Sarlak? ? AI ???: Bald Eagle Point? + ? ????: Gorgon Point? AI ???: Gorgon Point? ? Escher? - ? Zen 6 10000: Medusa (2026)? 6th Gen: Venice==Weisshorn + ? Zen 6 10000: Medusa (2026)? 6th Gen: Venice{==Weisshorn} + Zen 6c 6th Gen: Monarch -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Ryzen = Desktop/Mobile @@ -359,6 +365,60 @@ e = lowest power 9W C = chromebook + EPYC numbering, generations 1-3: + 1st digit: product series + 3 = embedded (socket SP4) + 7 = server (socket SP3) + 2nd digit: core count (c): + 1 = 4 + 2 = 8-16 + 3 = 16-24 (12 for embedded) + 4 = 24-32 (16 for embedded) + 5 = 32-48 + 6 = 48-64 + 7 = 64 + F = 8-24 (high per-core performance) + H = 64 + 3rd digit: performance (p): + 0,1 = entry-level + 3 = low to mid + 4,5,6 = mid + 7,8 = high + F = high per-core performance + H = best + 4th digit: generation + Suffixes: + P = single-processor + X = 3D V-cache + + EPYC numbering, generations 4-5: + 1st digit: product series + 9 = server (socket SP5) + 2nd digit: core count (c): + 0 = 8 + 1 = 16 + 2 = 24 + 3 = 32-36 + 4 = 48 + 5 = 64-72 + 6 = 84-96 + 7 = 112-128 + 8 = 144-160 + 9 = 192 + 3rd digit: performance (p): + 0,1 = entry-level + 2,3 = low to mid + 4 = mid + 5,6 = high + 7 = high per-core performance + 8 = extreme, large L3 cache + 4th digit: generation + Suffixes: + F = high per-core performance + P = single-processor + S = single-threaded + X = 3D V-cache + ====================================================================================================================================== Zhaoxin (VIA + Shanghai Municipal Government), began ~2013: diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250316/Makefile new/cpuid-20250513/Makefile --- old/cpuid-20250316/Makefile 2025-03-17 03:35:54.000000000 +0100 +++ new/cpuid-20250513/Makefile 2025-05-13 13:10:50.000000000 +0200 @@ -9,7 +9,7 @@ INSTALL_STRIP=-s PACKAGE=cpuid -VERSION=20250316 +VERSION=20250513 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250316/cpuid.c new/cpuid-20250513/cpuid.c --- old/cpuid-20250316/cpuid.c 2025-03-13 15:28:39.000000000 +0100 +++ new/cpuid-20250513/cpuid.c 2025-05-13 13:10:09.000000000 +0200 @@ -1891,10 +1891,6 @@ /* Hybrid special case with Pentium Gold branding, instead of Core */ #define Pa (is_intel && stash->br.pentium && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20) #define Pc (is_intel && stash->br.pentium && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40) -/* Hybrid special cases where "Core" implies a different branding than usual, - such as the Core i3 N-Series */ -#define Ia (is_intel && stash->br.core && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20) -#define Ic (is_intel && stash->br.core && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40) /* ** AMD major queries: @@ -2319,7 +2315,12 @@ FMQ ( 0, 6, 12, 6, Ha, *u = "Skymont", *p = "TSMC N3"); FMQ ( 0, 6, 12, 6, Hc, *u = "Lion Cove", *p = "TSMC N3"); // Whatever uarch namess are correct for (0,6),(12,12) Panther Lake (expect Intel 18A) + // P-core: News articles suggest Cougar Cove. + // E-core: Old speculation is Darkmont, news articles say Skymont, LX* says Crestmont(!) FM ( 0, 6, 12,15, *u = "Emerald Rapids", *ciu = TRUE, *f = "Raptor Cove, optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX* + // Whatever uarch names are correct for (0,6),(13,5) Wildcat Lake (expect Intel 18A) + // Speculation is that it's similar to Panther Lake, so Cougar Cove + Darkmont. + FM ( 0, 6, 13, 7, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // LX* FM ( 0, 6, 13,13, *u = "Darkmont", *p = "Intel 18A"); // MSR_CPUID_table*; LX* F ( 0, 7, *u = "Itanium"); FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu = TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org @@ -3606,7 +3607,7 @@ FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill)"); // no spec update; only MSR_CPUID_table* & SSG* so far. // SSG* provides the 4,5,7 steppings. - FMS ( 0, 6, 8, 6, 4, "Intel Atom P5900 (Snow Ridge B0)"); + FMS ( 0, 6, 8, 6, 4, "Intel Atom P5900 (Snow Rid<ge B0)"); FMS ( 0, 6, 8, 6, 5, "Intel Atom P5900 (Snow Ridge B1)"); FMS ( 0, 6, 8, 6, 7, "Intel Atom P5300 / P5700 (Snow Ridge) / C5000 (Parker Ridge)"); FM ( 0, 6, 8, 6, "Intel Atom (Snow Ridge/Parker Ridge)"); @@ -3880,15 +3881,26 @@ FM ( 0, 6, 10,10, "Intel (unknown type) (Meteor Lake-M)"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,11, "Intel (unknown type) (Meteor Lake-N)"); // DPTF* FM ( 0, 6, 10,12, "Intel (unknown type) (Meteor Lake-S)"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,13, "Intel (unknown type) (Granite Rapids)"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,14, "Intel (unknown type) (Granite Rapids)"); // MSR_CPUID_table* - FMSQ( 0, 6, 10,15, 3, sX, "Intel Xeon 6 6700E-Series (Sierra Forest C0)"); // stepping from ILPMDF* 2025-02-11 + // Intel doc 835486 + // ILPMDF* 20250512 names stepping 1 as B0/H0. + FMSQ( 0, 6, 10,13, 1, sX, "Intel Xeon 6 6x00 (Granite Rapids B0/H0)"); + FMS ( 0, 6, 10,13, 1, "Intel (unknown type) (Granite Rapids B0/H0)"); + FMQ ( 0, 6, 10,13, sX, "Intel Xeon 6 6x00 (Granite Rapids)"); + FM ( 0, 6, 10,13, "Intel (unknown type) (Granite Rapids)"); + // Intel doc 843306 + // Mentions stepping 1, but with no name. + FMQ ( 0, 6, 10,14, sX, "Intel Xeon 6 6x00P (Granite Rapids)"); + FM ( 0, 6, 10,14, "Intel (unknown type) (Granite Rapids)"); + // Intel doc 820922 + FMSQ( 0, 6, 10,15, 3, sX, "Intel Xeon 6 6700E (Sierra Forest C0)"); // stepping from ILPMDF* 2025-02-11 FMS ( 0, 6, 10,15, 3, "Intel (unknown type) (Sierra Forest C0)"); // stepping from ILPMDF* 2025-02-11 FMQ ( 0, 6, 10,15, sX, "Intel Xeon 6 (Sierra Forest)"); // MSR_CPUID_table*; sample from CCRT FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); // MSR_CPUID_table*; sample from CCRT & (engr?) sample via instlatx64 from Komachi_ENSAKA // Intel doc 834774 - FMSQ( 0, 6, 11, 5, 0, dU, "Intel Core Ultra 2xxS (Arrow Lake-U A1)"); - FMS ( 0, 6, 11, 5, 0, "Intel (unknown type) (Arrow Lake-U A1)"); + // 834774 names stepping 0 as A0. ILPMDF* 20250512 names it as A1. + // Preferring 834774. + FMSQ( 0, 6, 11, 5, 0, dU, "Intel Core Ultra 2xxS (Arrow Lake-U A0)"); + FMS ( 0, 6, 11, 5, 0, "Intel (unknown type) (Arrow Lake-U A0)"); FMQ ( 0, 6, 11, 5, dU, "Intel Core Ultra 2xxS (Arrow Lake-U)"); FM ( 0, 6, 11, 5, "Intel (unknown type) (Arrow Lake-U)"); // Grand Ridge: Atom P6900 name from: @@ -3901,12 +3913,12 @@ FMSQ( 0, 6, 11, 7, 0, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX A0)"); // Coreboot* FMSQ( 0, 6, 11, 7, 0, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX A0)"); // Coreboot* FMS ( 0, 6, 11, 7, 0, "Intel (unknown type) (Raptor Lake-S/HX A0)"); // Coreboot* - FMSQ( 0, 6, 10, 7, 1, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E B0)"); + FMSQ( 0, 6, 11, 7, 1, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E B0)"); FMSQ( 0, 6, 11, 7, 1, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX B0)"); FMSQ( 0, 6, 11, 7, 1, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX B0)"); FMSQ( 0, 6, 11, 7, 1, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX B0)"); FMS ( 0, 6, 11, 7, 1, "Intel (unknown type) (Raptor Lake-S/HX B0)"); - FMQ ( 0, 6, 10, 7, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E)"); + FMQ ( 0, 6, 11, 7, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E)"); FMQ ( 0, 6, 11, 7, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX)"); FMQ ( 0, 6, 11, 7, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX)"); FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX)"); @@ -3926,6 +3938,7 @@ FM ( 0, 6, 11,10, "Intel (unknown type) (Raptor Lake-P)"); FM ( 0, 6, 11,12, "Intel (unknown type) (Lunar Lake)"); // Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def // Intel doc 829568 + // ILPMDF* 20250512 confirms stepping 1 as B0. FMSQ( 0, 6, 11,13, 0, dU, "Intel Core Ultra 2xxV (Lunar Lake A0)"); FMS ( 0, 6, 11,13, 0, "Intel (unknown type) (Lunar Lake A0)"); FMSQ( 0, 6, 11,13, 1, dU, "Intel Core Ultra 2xxV (Lunar Lake B0)"); @@ -3935,21 +3948,21 @@ // Intel doc 764616 // ILPMDF* 20231114 claims this covers stepping N0 as well as A0. // ILPMDF* 20240910 claims that this now also covers Twin Lake N0. - // Is Twin Lake (Intel N250) distinguishable from - // Alder Lake-N (Intel N50-N200) only via branding? - // Does it also apply to any i3-N300 & Atom x7000E CPUs? + // Twin Lake & Alder Lake-N are nearly indistuishable. The only + // difference I see is branding, the branding prefix keeps changing, and + // the rules are too subtle. Best guess right now: + // ADL-N = (Nxy, Nx0y) (e.g. Intel N95, + // Intel Core i3-N305, + // TWL = (Nx5y) (e.g. Intel Core 3 N355) + // At least the Atom x7000E appears to be only Alder Lake-N. FMSQ( 0, 6, 11,14, 0, da, "Intel Atom x7000E (Alder Lake-N A0/N0)"); // ILPMDF* 20230512 - FMSQ( 0, 6, 11,14, 0, Ia, "Intel Core i*-N300 N-Series E-core (Alder Lake-N A0/N0)"); - FMSQ( 0, 6, 11,14, 0, Ic, "Intel Core i*-N300 N-Series P-core (Alder Lake-N A0/N0)"); // possibly no P-cores ever for this model - FMSQ( 0, 6, 11,14, 0, Ha, "Intel N-Series E-core (Alder Lake-N A0/N0 / Twin Lake N0)"); - FMSQ( 0, 6, 11,14, 0, Hc, "Intel N-Series P-core (Alder Lake-N A0/N0 / Twin Lake N0)"); // possibly no P-cores ever for these model - FMS ( 0, 6, 11,14, 0, "Intel N-Series / Atom x7000E (Alder Lake-N A0/N0 / Twin Lake N0)"); + FMSQ( 0, 6, 11,14, 0, Ha, "Intel N-Series / Core N-Series E-core (Alder Lake-N A0/N0 / Twin Lake N0)"); + FMSQ( 0, 6, 11,14, 0, Hc, "Intel N-Series / Core N-Series P-core (Alder Lake-N A0/N0 / Twin Lake N0)"); // probably no P-cores ever for these model + FMS ( 0, 6, 11,14, 0, "Intel N-Series / Core N-Series / Atom x7000E (Alder Lake-N A0/N0 / Twin Lake N0)"); FMQ ( 0, 6, 11,14, da, "Intel Atom x7000E (Alder Lake-N)"); // ILPMDF* 20230512 - FMQ ( 0, 6, 11,14, Ia, "Intel Core i*-N300 N-Series E-core (Alder Lake-N)"); - FMQ ( 0, 6, 11,14, Ic, "Intel Core i*-N300 N-Series P-core (Alder Lake-N)"); // possibly no P-cores ever for this model - FMQ ( 0, 6, 11,14, Ha, "Intel N-Series E-core (Alder Lake-N / Twin Lake)"); - FMQ ( 0, 6, 11,14, Hc, "Intel N-Series P-core (Alder Lake-N / Twin Lake)"); // possibly no P-cores ever for this model - FM ( 0, 6, 11,14, "Intel N-Series / Atom x7000E (Alder Lake-N / Twin Lake)"); + FMQ ( 0, 6, 11,14, Ha, "Intel N-Series / Core N-Series E-core (Alder Lake-N / Twin Lake)"); + FMQ ( 0, 6, 11,14, Hc, "Intel N-Series / Core N-Series P-core (Alder Lake-N / Twin Lake)"); // probably no P-cores ever for this model + FM ( 0, 6, 11,14, "Intel N-Series / Core N-Series / Atom x7000E (Alder Lake-N / Twin Lake)"); // Intel doc 740518 provides steppings 2 & 5, but without names // Intel doc 743844 provides steppings 2 & 5, with names: C0 & H0. // ILPMDF* 20231114 confirms steppings C0 & H0. @@ -3966,11 +3979,13 @@ FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P)"); FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/HX/P)"); // Intel doc 834774 + // ILPMDF* 20250512 confirms stepping 2 as A1. FMSQ( 0, 6, 12, 5, 2, dU, "Intel Core Ultra 2xxS (Arrow Lake-H A1)"); FMS ( 0, 6, 12, 5, 2, "Intel (unknown type) (Arrow Lake-H A1)"); FMQ ( 0, 6, 12, 5, dU, "Intel Core Ultra 2xxS (Arrow Lake-H)"); FM ( 0, 6, 12, 5, "Intel (unknown type) (Arrow Lake)"); // Intel doc 834774 + // ILPMDF* 20250512 confirms stepping 2 as B0 (doesn't mention A0). FMSQ( 0, 6, 12, 6, 2, dU, "Intel Core Ultra 2xxS (Arrow Lake-S A0/B0)"); FMS ( 0, 6, 12, 6, 2, "Intel (unknown type) (Arrow Lake-S A0/B0)"); FMQ ( 0, 6, 12, 6, dU, "Intel Core Ultra 2xxS (Arrow Lake-S)"); @@ -3984,6 +3999,9 @@ FMS ( 0, 6, 12,15, 2, "Intel Xeon (unknown type) (Emerald Rapids A1/R1)"); FMQ ( 0, 6, 12,15, sS, "Intel Xeon Scalable (5th Gen) Bronze/Silver/Gold/Platinum (Emerald Rapids)"); FM ( 0, 6, 12,15, "Intel Xeon (unknown type) (Emerald Rapids)"); + FMS ( 0, 6, 13, 5, 0, "Intel (unknown type) (Wildcat Lake A0)"); // Coreboot* + FM ( 0, 6, 13, 5, "Intel (unknown type) (Wildcat Lake)"); // Coreboot* + FM ( 0, 6, 13, 7, "Intel (unknown type) (Bartlett Lake)"); // LX* FM ( 0, 6, 13,13, "Intel (unknown type) (Clearwater Forest)"); // MSR_CPUID_table* FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); @@ -4923,6 +4941,7 @@ FMm (10,15, 0, 0, "AMD EPYC (3rd Gen) (Milan %c%u)"); // 56683 FMm (10,15, 0, 8, "AMD Ryzen Threadripper 5000 (Chagall %c%u)"); // undocumented, but sample from CCRT FMm (10,15, 1, 0, "AMD EPYC (4th Gen) (Genoa %c%u)"); // PPR 57095, PPR 55901 + // The AMD Ryzen Threadripper Pro CPU (Family 19h Model 18h and ... FMm (10,15, 1, 8, "AMD Ryzen Threadripper 7000 (Storm Peak %c%u)"); // undocumented, but samples from instlatx64 FMm (10,15, 2, 0, "AMD Ryzen 5000 (Vermeer %c%u)"); // PPR 56214 FMm (10,15, 3, 0, "AMD Ryzen (Badami %c%u)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ @@ -4936,9 +4955,11 @@ FMm (10,15, 9, 0, "AMD Instinct MI300A"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam FMm (10,15, 10, 0, "AMD EPYC (4th Gen) (Bergamo/Siena %c%u)"); // PPR 57228 F (10,15, "AMD (unknown model)"); - FMm (11,15, 0, 0, "AMD EPYC (5th Gen) (Turin %c%u)"); // PPR 57238 - FMm (11,15, 0, 8, "AMD EPYC (5th Gen) (Turin %c%u)"); // PPR 57238 - FMm (11,15, 1, 0, "AMD EPYC (5th Gen) (Sorano %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 0, 0, "AMD EPYC (5th Gen) (Turin %c%u)"); // PPR 57238, 58251 + // https://docs.amd.com/v/u/en-US/dh300-amd-ryzen-threadripper-tr5: + // The AMD Ryzen Threadripper Pro CPU (... and Model 1Ah Model 08h) + FMm (11,15, 0, 8, "AMD EPYC (5th Gen) (Shimada Peak %c%u)"); + FMm (11,15, 1, 0, "AMD EPYC (5th Gen) (Sorano %c%u)"); // PPR 58730, LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 1, 8, "AMD EPYC (5th Gen) (Sorano %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian // Are all these Strix Point's Ryzen AI 300 CPU's? // I suspect the latter ones are not. @@ -5204,6 +5225,8 @@ FMS (9,15, 0, 0, 2, "Hygon Dhyana (A2)"); FMS (9,15, 0, 1, 1, "Hygon Dhyana (B1)"); FMS (9,15, 0, 2, 2, "Hygon Dhyana (C2)"); + // (9,15),(0,4),1 is branded as Hygon C86-4G; perhaps Dhyana (E1)? + // (9,15),(0,6),0 is branded as Hygon C86-4G; perhaps Dhyana (G0)? DEFAULT ("unknown"); return result; @@ -6619,7 +6642,9 @@ print_7_1_ecx(unsigned int value) { static named_item names[] - = { { "RDMSR/WRMSRNS immediates supported" , 5, 5, bools }, + = { { "asymmetric RDT-M monitoring" , 0, 0, bools }, + { "asymmetric RDT-A allocation" , 1, 1, bools }, + { "RDMSR/WRMSRNS immediates supported" , 5, 5, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); @@ -7145,6 +7170,7 @@ { "SGX ENCLU EVERIFYREPORT2" , 7, 7, bools }, { "SGX ENCLS EUPDATESVN" , 10, 10, bools }, { "SGX ENCLU EDECCSSA" , 11, 11, bools }, + { "256BITSGX EGETKEY256 & EREPORT2" , 12, 12, bools }, }; print_names(value, names, LENGTH(names), @@ -7532,6 +7558,24 @@ NULL, NULL, NULL, NULL, /* 40h => */ "Intel Core" }; + // For coretype == 0x20 (Atom): + // LX* claims: + // native_model == 2 => Crestmont + // native_model == 3 => Skymont + // For all my samples: + // native_model == 0 for Tremont + // native_model == 1 for Gracemont + // native_model == 2 for Crestmont + // native_model == 3 for Skymont + // Is this pattern reliable? + // For coretype == 0x40 (Core): + // For all my samples: + // native_model == 0 for Sunny Cove + // native_model == 1 for {Golden,Raptor} Cove (inconsistent) + // native_model == 2 for Redwood Cove + // native_model == 3 for Lion Cove + // This doesn't seem reliable/consistent. + static named_item names[] = { { "native model ID of core" , 0, 23, NIL_IMAGES }, { "core type" , 24, 31, coretypes }, @@ -7804,6 +7848,161 @@ } static void +print_27_0_edx(unsigned int value) +{ + static named_item names[] + = { { "supports L3 Cache Intel RDT monitoring" , 1, 1, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 0); +} + +static void +print_27_1_eax(unsigned int value) +{ + static named_item names[] + = { { "counter width" , 0, 7, MINUS24_IMAGES }, + { "IA32_QM_CTR overflow present" , 8, 8, bools }, + { "non-CPU agent Intel RDT CMT support" , 9, 9, bools }, + { "non-CPU agent Intel RDT MBM support" , 10, 10, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 38); +} + +static void +print_27_1_edx(unsigned int value) +{ + static named_item names[] + = { { "supports L3 occupancy monitoring" , 0, 0, bools }, + { "supports L3 total bandwidth monitoring" , 1, 1, bools }, + { "supports L3 local bandwidth monitoring" , 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 38); +} + +static void +print_28_0_ebx(unsigned int value) +{ + static named_item names[] + = { { "supports L3 Cache Allocation Technology" , 1, 1, bools }, + { "supports L2 Cache Allocation Technology" , 2, 2, bools }, + { "supports Memory Bandwidth Allocation" , 3, 3, bools }, + { "supports Cache Bandwidth Allocation" , 5, 5, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 38); +} + +static void +print_28_1_eax(unsigned int value) +{ + static named_item names[] + = { { "length of capacity bit mask" , 0, 7, MINUS1_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_1_ecx(unsigned int value) +{ + static named_item names[] + = { { "supports L3 CAT for non-CPU agents" , 1, 1, bools }, + { "supports L3 Code & Data Prioritization" , 2, 2, bools }, + { "supports non-contiguous capacity bitmask", 3, 3, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_2_eax(unsigned int value) +{ + static named_item names[] + = { { "length of capacity bit mask" , 0, 4, MINUS1_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_2_ecx(unsigned int value) +{ + static named_item names[] + = { { "supports L2 Code & Data Prioritization" , 2, 2, bools }, + { "supports non-contiguous capacity bitmask", 3, 3, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_3_eax(unsigned int value) +{ + static named_item names[] + = { { "maximum MBA throttling value supported" , 0, 11, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_3_ecx(unsigned int value) +{ + static named_item names[] + = { { "supports per-thread MBA controls" , 0, 0, bools }, + { "delay response is linear" , 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_5_eax(unsigned int value) +{ + static named_item names[] + = { { "maximum core throttling value supported" , 0, 11, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_5_ecx(unsigned int value) +{ + static named_item names[] + = { { "bandwidth response is approx linear" , 3, 3, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_28_n_edx(unsigned int value) +{ + static named_item names[] + = { { "highest COS number supported" , 0, 15, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void print_20000001_edx(unsigned int value) { // I found a vague reference to this leaf in Intel Xeon Phi Coprocessor @@ -7989,6 +8188,8 @@ { "supervisor shadow stack" , 6, 6, bools }, { "architectural PMU" , 7, 7, bools }, { "exception trap intercept" , 8, 8, bools }, + { "dispatch intr injection available" , 9, 9, bools }, // LX* + { "GHCB root mapping available" , 10, 10, bools }, // LX* }; printf(" hypervisor power management features (0x%08x/ecx):\n", reg); @@ -9258,7 +9459,7 @@ { "extended LVT AVIC access changes" , 27, 27, bools }, { "guest VMCB addr check" , 28, 28, bools }, { "bus lock threshold" , 29, 29, bools }, - { "idlt HLT intercept" , 30, 30, bools }, + { "idle HLT intercept" , 30, 30, bools }, { "EXITINFO1 non-interceptible shutdown" , 31, 31, bools }, }; @@ -10817,6 +11018,54 @@ } else { print_reg_raw(reg, sub, words); } + } else if (reg == 0x27) { + if (sub == 0) { + printf(" Intel RDT Asymmetric (0x27/0):\n"); + print_27_0_edx(words[WORD_EDX]); + printf(" maximum RMID range = 0x%08x (%u)\n", + words[WORD_EBX], words[WORD_EBX]); + } else if (sub == 1) { + printf(" Intel RDT Asymmetric: L3 Cache (0x27/1):\n"); + print_27_1_eax(words[WORD_EAX]); + print_27_1_edx(words[WORD_EDX]); + printf(" IA32_QM_CTR conversion factor = 0x%08x (%u)\n", + words[WORD_EBX], words[WORD_EBX]); + printf(" maximum RMID range = 0x%08x (%u)\n", + words[WORD_ECX], words[WORD_ECX]); + } else { + print_reg_raw(reg, sub, words); + } + } else if (reg == 0x28) { + if (sub == 0) { + printf(" Intel RDT-A Asymmetric (0x28/0):\n"); + print_28_0_ebx(words[WORD_EBX]); + } else if (sub == 1) { + printf(" Intel RDT-A Asymmetric: L3 Cache (0x28/1):\n"); + print_28_1_eax(words[WORD_EAX]); + print_28_1_ecx(words[WORD_ECX]); + print_28_n_edx(words[WORD_EDX]); + printf(" alloc units isolation/contention map = 0x%08x\n", + words[WORD_EBX]); + } else if (sub == 2) { + printf(" Intel RDT-A Asymmetric: L2 Cache (0x28/2):\n"); + print_28_2_eax(words[WORD_EAX]); + print_28_2_ecx(words[WORD_ECX]); + print_28_n_edx(words[WORD_EDX]); + printf(" alloc units isolation/contention map = 0x%08x\n", + words[WORD_EBX]); + } else if (sub == 3) { + printf(" Intel RDT-A Asymmetric: Memory Bandwidth (0x28/3):\n"); + print_28_3_eax(words[WORD_EAX]); + print_28_3_ecx(words[WORD_ECX]); + print_28_n_edx(words[WORD_EDX]); + } else if (sub == 5) { + printf(" Intel RDT-A Asymmetric: Cache Bandwidth (0x28/5):\n"); + print_28_5_eax(words[WORD_EAX]); + print_28_5_ecx(words[WORD_ECX]); + print_28_n_edx(words[WORD_EDX]); + } else { + print_reg_raw(reg, sub, words); + } } else if (reg == 0x20000000) { // max already set to words[WORD_EAX] in calling function } else if (reg == 0x20000001) { @@ -11779,10 +12028,7 @@ real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x1e) { - // Leaf 0x1e having sub-leaves seems to be an afterthought. The - // leaf doesn't indicate its max subleaf in any way, so a reader - // must "just know". - unsigned int max_subs = 1; + unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); @@ -11827,6 +12073,27 @@ if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } + } else if (reg == 0x27) { + // This leafs provides no max, so assume it allows only the + // documented 2 sub-leaves. + unsigned int max_subs = 1; + unsigned int sub = 0; + for (;;) { + print_reg(reg, sub, words, opts, &stash); + sub++; + if (sub > max_subs) break; + real_get(cpuid_fd, reg, sub, words, FALSE); + } + } else if (reg == 0x28) { + unsigned int mask = words[WORD_EBX]; + print_reg(reg, 0, words, opts, &stash); + unsigned int sub; + for (sub = 1; sub < 32; sub++) { + if (mask & (1 << sub)) { + real_get(cpuid_fd, reg, sub, words, FALSE); + print_reg(reg, sub, words, opts, &stash); + } + } } else if (reg == 0x80000026) { print_reg(reg, 0, words, opts, &stash); unsigned int sub; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250316/cpuid.man new/cpuid-20250513/cpuid.man --- old/cpuid-20250316/cpuid.man 2025-03-17 03:36:43.000000000 +0100 +++ new/cpuid-20250513/cpuid.man 2025-05-13 13:19:16.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20250316 2025/03/16 20:35:23 todd $ +.\" $Id: cpuid.man,v 20250513 2025/05/13 05:18:57 todd $ .\" -.TH CPUID 1 "16 Mar 2025" "20250316" +.TH CPUID 1 "13 May 2025" "20250513" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -557,10 +557,17 @@ 793902: 5th Gen Intel Xeon Processor Scalable Family, Codename Emerald Rapids Specification Update .br +820922: Intel Xeon 6700-Series Processor with E-Cores Specification Update +.br 827538: Intel Core Ultra 200V Series Processors Specification Update .br 834774: Intel Core Ultra 200S Series Processors Specification Update .br +835486: Intel Xeon 6900/6700/6500-Series Processors with P-Cores +Specification Update +.br +843306: Intel Xeon 6700P-B/6500P-B-Series SoC with P-Cores Specification Update +.br Intel Microcode Update Guidance .br Branch History Injection and Intra-mode Branch Target Injection / @@ -693,8 +700,12 @@ .br 58015: AMD EPYC 9004 Series Architecture Overview .br +58251: AMD Revision Guide for AMD Family 1Ah Models 00h-0Fh Processors +.br 58268: AMD EPYC 8004 Series Architecture Overview .br +58730: AMD Revision Guide for AMD Family 1Ah Models 10h-1Fh Processors +.br AMD64 Technology Indirect Branch Control Extension (White Paper), Revision 4.10.18 .br diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250316/cpuid.spec new/cpuid-20250513/cpuid.spec --- old/cpuid-20250316/cpuid.spec 2025-03-17 03:38:21.000000000 +0100 +++ new/cpuid-20250513/cpuid.spec 2025-05-13 13:21:24.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20250316 +%define version 20250513 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
