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Package is "llvm11" Wed Aug 18 08:56:01 2021 rev:11 rq:912486 version:11.0.1 Changes: -------- --- /work/SRC/openSUSE:Factory/llvm11/llvm11.changes 2021-07-03 20:51:22.240527932 +0200 +++ /work/SRC/openSUSE:Factory/.llvm11.new.1899/llvm11.changes 2021-08-18 08:56:49.894910024 +0200 @@ -1,0 +2,6 @@ +Mon Aug 16 08:36:03 UTC 2021 - Richard Biener <[email protected]> + +- Add llvm-systemz-args-handling.patch to fix s390 argument handling. + [bsc#1189189] + +------------------------------------------------------------------- New: ---- llvm-systemz-args-handling.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ llvm11.spec ++++++ --- /var/tmp/diff_new_pack.9m9HtA/_old 2021-08-18 08:56:51.122908580 +0200 +++ /var/tmp/diff_new_pack.9m9HtA/_new 2021-08-18 08:56:51.126908575 +0200 @@ -136,6 +136,8 @@ Patch33: CMake-Look-up-target-subcomponents-in-LLVM_AVAILABLE_LIBS.patch # Fix build with linux-glibc-devel 5.13. (https://reviews.llvm.org/D102059) Patch34: compiler-rt-Remove-cyclades-inclusion-in-sanitizer.patch +# Fix SystemZ stack temporary overflow. (https://reviews.llvm.org/D97514) +Patch35: llvm-systemz-args-handling.patch BuildRequires: binutils-devel >= 2.21.90 BuildRequires: cmake BuildRequires: fdupes @@ -562,6 +564,7 @@ %patch27 -p2 %patch32 -p2 %patch33 -p2 +%patch35 -p2 pushd clang-%{_version}.src %patch2 -p1 ++++++ llvm-systemz-args-handling.patch ++++++ >From 0193a7da8bdaa9ffcc5bdefd5516c162bb26ab6b Mon Sep 17 00:00:00 2001 From: Jonas Paulsson <[email protected]> Date: Thu, 25 Feb 2021 16:05:43 -0600 Subject: [PATCH] [SystemZ] Assign the full space for promoted and split outgoing args. When a large "irregular" (e.g. i96) integer call argument is converted to indirect, 64-bit parts are stored to the stack. The full stack space (e.g. i128) was not allocated prior to this patch, but rather just the exact space of the original type. This caused neighboring values on the stack to be overwritten. Thanks to Josh Stone for reporting this. Review: Ulrich Weigand Fixes https://bugs.llvm.org/show_bug.cgi?id=49322 Differential Revision: https://reviews.llvm.org/D97514 (cherry picked from commit 52bbbf4d4459239e0f461bc302ada89e2c5d07fc) --- .../Target/SystemZ/SystemZISelLowering.cpp | 22 ++++++-- llvm/test/CodeGen/SystemZ/args-11.ll | 54 +++++++++++++++++++ 2 files changed, 72 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/args-11.ll diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 9ace36f344a5..270134d84c61 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -1550,6 +1550,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI, bool IsVarArg = CLI.IsVarArg; MachineFunction &MF = DAG.getMachineFunction(); EVT PtrVT = getPointerTy(MF.getDataLayout()); + LLVMContext &Ctx = *DAG.getContext(); // Detect unsupported vector argument and return types. if (Subtarget.hasVector()) { @@ -1559,7 +1560,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI, // Analyze the operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; - SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx); ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); // We don't support GuaranteedTailCallOpt, only automatically-detected @@ -1584,14 +1585,25 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI, if (VA.getLocInfo() == CCValAssign::Indirect) { // Store the argument in a stack slot and pass its address. - SDValue SpillSlot = DAG.CreateStackTemporary(Outs[I].ArgVT); + unsigned ArgIndex = Outs[I].OrigArgIndex; + EVT SlotVT; + if (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) { + // Allocate the full stack space for a promoted (and split) argument. + Type *OrigArgType = CLI.Args[Outs[I].OrigArgIndex].Ty; + EVT OrigArgVT = getValueType(MF.getDataLayout(), OrigArgType); + MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); + unsigned N = getNumRegistersForCallingConv(Ctx, CLI.CallConv, OrigArgVT); + SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); + } else { + SlotVT = Outs[I].ArgVT; + } + SDValue SpillSlot = DAG.CreateStackTemporary(SlotVT); int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); MemOpChains.push_back( DAG.getStore(Chain, DL, ArgValue, SpillSlot, MachinePointerInfo::getFixedStack(MF, FI))); // If the original argument was split (e.g. i128), we need // to store all parts of it here (and pass just one address). - unsigned ArgIndex = Outs[I].OrigArgIndex; assert (Outs[I].PartOffset == 0); while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) { SDValue PartValue = OutVals[I + 1]; @@ -1601,6 +1613,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI, MemOpChains.push_back( DAG.getStore(Chain, DL, PartValue, Address, MachinePointerInfo::getFixedStack(MF, FI))); + assert((PartOffset + PartValue.getValueType().getStoreSize() <= + SlotVT.getStoreSize()) && "Not enough space for argument part!"); ++I; } ArgValue = SpillSlot; @@ -1694,7 +1708,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI, // Assign locations to each value returned by this call. SmallVector<CCValAssign, 16> RetLocs; - CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); + CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, Ctx); RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); // Copy all of the result registers out of their specified physreg. diff --git a/llvm/test/CodeGen/SystemZ/args-11.ll b/llvm/test/CodeGen/SystemZ/args-11.ll new file mode 100644 index 000000000000..b355f9d6da15 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/args-11.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; Test outgoing promoted arguments that are split (and passed by reference). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; The i96 arg is promoted to i128 and should get the full stack space. +declare void @fn1(i96) +define i32 @fn2() { +; CHECK-LABEL: fn2: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r14, %r15, 112(%r15) +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -184 +; CHECK-NEXT: .cfi_def_cfa_offset 344 +; CHECK-NEXT: mvhi 180(%r15), -1 +; CHECK-NEXT: mvghi 168(%r15), 0 +; CHECK-NEXT: la %r2, 160(%r15) +; CHECK-NEXT: mvghi 160(%r15), 0 +; CHECK-NEXT: brasl %r14, fn1@PLT +; CHECK-NEXT: l %r2, 180(%r15) +; CHECK-NEXT: lmg %r14, %r15, 296(%r15) +; CHECK-NEXT: br %r14 + %1 = alloca i32 + store i32 -1, i32* %1 + call void @fn1(i96 0) + %2 = load i32, i32* %1 + ret i32 %2 +} + +declare void @fn3(i136) +define i32 @fn4() { +; CHECK-LABEL: fn4: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r14, %r15, 112(%r15) +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -192 +; CHECK-NEXT: .cfi_def_cfa_offset 352 +; CHECK-NEXT: mvhi 188(%r15), -1 +; CHECK-NEXT: mvghi 176(%r15), 0 +; CHECK-NEXT: mvghi 168(%r15), 0 +; CHECK-NEXT: la %r2, 160(%r15) +; CHECK-NEXT: mvghi 160(%r15), 0 +; CHECK-NEXT: brasl %r14, fn3@PLT +; CHECK-NEXT: l %r2, 188(%r15) +; CHECK-NEXT: lmg %r14, %r15, 304(%r15) +; CHECK-NEXT: br %r14 + %1 = alloca i32 + store i32 -1, i32* %1 + call void @fn3(i136 0) + %2 = load i32, i32* %1 + ret i32 %2 +} -- 2.26.2
