Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package CoreFreq for openSUSE:Factory checked in at 2022-08-23 14:29:37 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old) and /work/SRC/openSUSE:Factory/.CoreFreq.new.2083 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq" Tue Aug 23 14:29:37 2022 rev:15 rq:998693 version:1.91.6 Changes: -------- --- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2022-06-23 10:25:44.207835594 +0200 +++ /work/SRC/openSUSE:Factory/.CoreFreq.new.2083/CoreFreq.changes 2022-08-23 14:29:48.771633432 +0200 @@ -1,0 +2,13 @@ +Mon Aug 22 15:48:08 UTC 2022 - Michael Pujos <[email protected]> + +- Update to version 1.91.6 + - [AMD/Zen][UMC] Fixed the Mem Clock and ECC regressions + - Designate the Package identifier in Power consumed readings + - [Intel/ADL/IMC] Guessing activated channel from the populated DIMM + - [AMD][UMC, IOMMU] Adding missing DID of family 19h devices + - [AMD_DataFabric_Cezanne] Removed the Experimental mode + - Intel/ADL/IMC: Fixing the Memory Channels count + - [AMD/Zen] Improved UMC mapping. Threadripper 3960X issue + - Avoid some NULL pointer strings during SMBIOS decoding + +------------------------------------------------------------------- Old: ---- CoreFreq-1.91.3.tar.gz New: ---- CoreFreq-1.91.6.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ CoreFreq.spec ++++++ --- /var/tmp/diff_new_pack.j0wiM4/_old 2022-08-23 14:29:49.331634603 +0200 +++ /var/tmp/diff_new_pack.j0wiM4/_new 2022-08-23 14:29:49.339634620 +0200 @@ -17,7 +17,7 @@ Name: CoreFreq -Version: 1.91.3 +Version: 1.91.6 Release: 0 Summary: CPU monitoring software designed for 64-bits processors License: GPL-2.0-or-later ++++++ CoreFreq-1.91.3.tar.gz -> CoreFreq-1.91.6.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/Makefile new/CoreFreq-1.91.6/Makefile --- old/CoreFreq-1.91.3/Makefile 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/Makefile 2022-08-12 12:41:43.000000000 +0200 @@ -174,7 +174,7 @@ "| make [all] [clean] [info] [help] [install] [module-install] |\n"\ "| |\n"\ "| CC=<COMPILER> |\n"\ - "| where <COMPILER> is cc, gcc [clang partial support] |\n"\ + "| where <COMPILER> is cc, gcc, clang |\n"\ "| |\n"\ "| WARNING=<ARG> |\n"\ "| where default argument is -Wall |\n"\ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/README.md new/CoreFreq-1.91.6/README.md --- old/CoreFreq-1.91.3/README.md 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/README.md 2022-08-12 12:41:43.000000000 +0200 @@ -364,7 +364,7 @@ | make [all] [clean] [info] [help] [install] [module-install] | | | | CC=<COMPILER> | -| where <COMPILER> is cc, gcc [clang partial support] | +| where <COMPILER> is cc, gcc, clang | | | | WARNING=<ARG> | | where default argument is -Wall | @@ -411,6 +411,15 @@ | | MSR_AMD_F17H_APERF | MSR_AMD_F17H_MPERF | | | ------------------------------------------------------- | | | +| Architectural Counters: | +| ------------------------------------------------------- | +| | Intel | AMD | | +| |----------- REG -----------|----------- REG -----------| | +| | ARCH_PMC=PCU | ARCH_PMC=L3 | | +| | | ARCH_PMC=PERF | | +| | | ARCH_PMC=UMC | | +| ------------------------------------------------------- | +| | | User Interface Layout: | | NO_HEADER=<F> NO_FOOTER=<F> NO_UPPER=<F> NO_LOWER=<F> | | when <F> is 1: don't build and display this area part | @@ -418,7 +427,7 @@ | when <F> is 1: build with background transparency | | | | Example: | -| make CC=gcc OPTIM_LVL=3 FEAT_DBG=1 | +| make CC=gcc OPTIM_LVL=3 FEAT_DBG=1 ARCH_PMC=PCU | | MSR_CORE_PERF_UCC=MSR_CORE_PERF_FIXED_CTR1 | | MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2 | | HWM_CHIPSET=W83627 MAX_FREQ_HZ=5350000000 | diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/corefreq-api.h new/CoreFreq-1.91.6/corefreq-api.h --- old/CoreFreq-1.91.3/corefreq-api.h 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/corefreq-api.h 2022-08-12 12:41:43.000000000 +0200 @@ -1356,11 +1356,11 @@ /* Source: AMD PPR for AMD Family 17h Models 18h & 20h Processors */ #define DID_AMD_17H_ZEN_APU_NB_IOMMU 0x15d1 /* Raven2 */ /* Source: AMD PPR for AMD Family 17h Model 60h Processors */ -#define DID_AMD_17H_ZEN2_APU_NB_IOMMU 0x1631 /* Renoir */ +/* Source: AMD PPR for AMD Family 19h Model 51h, Rev A1 Processors */ +#define DID_AMD_17H_ZEN2_APU_NB_IOMMU 0x1631 /* Renoir/Cezanne */ #define DID_AMD_17H_FIREFLIGHT_NB_IOMMU 0x15f9 /* FireFlight */ #define DID_AMD_17H_ARDEN_NB_IOMMU 0x1627 /* Arden */ -/* Source: AMD PPR for AMD Family 19h Model 51h, Rev A1 Processors */ -#define DID_AMD_19H_CEZANNE_NB_IOMMU 0x1631 /* Cezanne */ + /* Source: /include/linux/pci_ids.h */ #define DID_AMD_17H_ZEPPELIN_DF_UMC 0x1460 /* Zeppelin */ #define DID_AMD_17H_RAVEN_DF_UMC 0x15e8 /* Raven */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/corefreq-cli-rsc-en.h new/CoreFreq-1.91.6/corefreq-cli-rsc-en.h --- old/CoreFreq-1.91.3/corefreq-cli-rsc-en.h 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/corefreq-cli-rsc-en.h 2022-08-12 12:41:43.000000000 +0200 @@ -663,7 +663,7 @@ "--------------------" #define RSC_LAYOUT_RULER_PWR_UNCORE_CODE_EN \ - "-RAM: . ( ) - Uncore: . ( ) - Package: . ( ) " \ + "-RAM: . ( ) - Uncore: . ( ) -- Pkg[ ]: . ( ) " \ "- Cores: . ( )-----------------------------------------" \ "------------------------------------------------------------" \ "------------------------------------------------------------" \ @@ -671,7 +671,7 @@ "--------------------" #define RSC_LAYOUT_RULER_PWR_SOC_CODE_EN \ - "-RAM: . ( ) --- SoC : . ( ) - Package: . ( ) " \ + "-RAM: . ( ) --- SoC : . ( ) -- Pkg[ ]: . ( ) " \ "- Cores: . ( )-----------------------------------------" \ "------------------------------------------------------------" \ "------------------------------------------------------------" \ @@ -679,7 +679,7 @@ "--------------------" #define RSC_LAYOUT_RULER_PWR_PLATFORM_CODE_EN \ - "-RAM: . ( ) Platform: . ( ) - Package: . ( ) " \ + "-RAM: . ( ) Platform: . ( ) -- Pkg[ ]: . ( ) " \ "- Cores: . ( )-----------------------------------------" \ "------------------------------------------------------------" \ "------------------------------------------------------------" \ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/corefreq-cli.c new/CoreFreq-1.91.6/corefreq-cli.c --- old/CoreFreq-1.91.3/corefreq-cli.c 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/corefreq-cli.c 2022-08-12 12:41:43.000000000 +0200 @@ -5458,9 +5458,11 @@ Setting.fahrCels ? 'F' : 'C' ); const int ldx = \ - sprintf( row, "\n" "%.*sPackage%.*sCores%.*sUncore%.*sMemory" \ + sprintf( row, "\n" "%.*sPackage[%c]%.*sCores%.*sUncore%.*sMemory" \ "%.*sPlatform" "\n" "Energy(J):", - 13, hSpace, 7, hSpace, 9, hSpace, 8, hSpace, 8, hSpace); + 13, hSpace, + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, + 4, hSpace, 9, hSpace, 8, hSpace, 8, hSpace); while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0) && (ldx > 0)) { @@ -5601,8 +5603,9 @@ " Accumulator Min Energy(J) Max" \ " Min Power(W) Max\n" ); const int ldx = \ - sprintf( row, "\nEnergy(J) Package%.*sCores%.*sUncore%.*sMemory\n", - 12, hSpace, 15, hSpace, 14, hSpace ); + sprintf( row, "\nEnergy(J) Package[%c]%.*sCores%.*sUncore%.*sMemory\n", + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, + 9, hSpace, 15, hSpace, 14, hSpace ); while (!BITVAL(Shutdown, SYNC) && (iter-- > 0) && (sdx > 0) && (ldx > 0)) { @@ -6766,6 +6769,9 @@ if ((li = strlen(RO(Shm)->SMB.Memory.PartNumber[slot])) > 0) { + if (li >= (4 * MC_MATY)) { + li = (4 * MC_MATY) - 1; + } StrFormat(str, CODENAME_LEN + 4 + 10, "%%%d.*s", (MC_MATX - 11) * MC_MATY); @@ -15796,6 +15802,9 @@ oRow = hPwrSoC.origin.row; } + LayerAt(layer,code, 45, oRow) = '0' + + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID; + LayerAt(layer,code, 14, oRow) = \ LayerAt(layer,code, 35, oRow) = \ LayerAt(layer,code, 57, oRow) = \ @@ -15899,6 +15908,9 @@ oRow = hPwrSoC.origin.row; } + LayerAt(layer,code, 45, oRow) = '0' + + RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID; + LayerAt(layer,code, 14, oRow) = \ LayerAt(layer,code, 35, oRow) = \ LayerAt(layer,code, 57, oRow) = \ @@ -18258,12 +18270,12 @@ #define CUST_INTEL(unit) " RAM:%8.4f(" COREFREQ_STRINGIFY(unit) ") -" \ "- SA:%8.4f(U)/%5.4f(V)" \ - " - Pkg:%8.4f(" COREFREQ_STRINGIFY(unit) ") - " \ + " - Pkg[%c]:%8.4f(" COREFREQ_STRINGIFY(unit) ") - " \ "%5.4f %5.4f %5.4f %8.4f %8.4f %8.4f -" #define CUST_AMD(unit) " RAM:%8.4f(" COREFREQ_STRINGIFY(unit) ") -" \ " SoC:%8.4f(" COREFREQ_STRINGIFY(unit) ")/%5.4f(V)" \ - " - Pkg:%8.4f(" COREFREQ_STRINGIFY(unit) ") - " \ + " - Pkg[%c]:%8.4f(" COREFREQ_STRINGIFY(unit) ") - " \ "%5.4f %5.4f %5.4f %8.4f %8.4f %8.4f" size_t Draw_AltMonitor_Custom_Energy_Joule(void) @@ -18279,6 +18291,8 @@ RO(Shm)->Proc.State.Energy[PWR_DOMAIN(RAM)].Current, RO(Shm)->Proc.State.Energy[PWR_DOMAIN(UNCORE)].Current, PFlop->Voltage.SOC, + + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, RO(Shm)->Proc.State.Energy[PWR_DOMAIN(PKG)].Current, RO(Shm)->Proc.State.Voltage.Limit[SENSOR_LOWEST], @@ -18313,6 +18327,8 @@ RO(Shm)->Proc.State.Power[PWR_DOMAIN(RAM)].Current, RO(Shm)->Proc.State.Power[PWR_DOMAIN(UNCORE)].Current, PFlop->Voltage.SOC, + + '0'+RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Topology.PackageID, RO(Shm)->Proc.State.Power[PWR_DOMAIN(PKG)].Current, RO(Shm)->Proc.State.Voltage.Limit[SENSOR_LOWEST], @@ -18359,7 +18375,7 @@ size_t len = Draw_AltMonitor_Custom_Matrix[Setting.jouleWatt](); - memcpy(&LayerAt(layer, code, LOAD_LEAD, row), &Buffer[ 0], len); + memcpy(&LayerAt(layer, code, 1, row), &Buffer[ 0], len); row += 1; return row; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/corefreqd.c new/CoreFreq-1.91.6/corefreqd.c --- old/CoreFreq-1.91.3/corefreqd.c 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/corefreqd.c 2022-08-12 12:41:43.000000000 +0200 @@ -3471,6 +3471,7 @@ case 0b000: return fallback; } + return fallback; } void SNB_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core)) @@ -6198,6 +6199,8 @@ case DID_AMD_17H_RENOIR_NB_IOMMU: case DID_AMD_17H_ZEN_APU_NB_IOMMU: case DID_AMD_17H_ZEN2_APU_NB_IOMMU: + case DID_AMD_17H_FIREFLIGHT_NB_IOMMU: + case DID_AMD_17H_ARDEN_NB_IOMMU: AMD_17h_IOMMU(RO(Shm), RO(Proc)); break; case DID_AMD_17H_ZEPPELIN_DF_UMC: @@ -6206,8 +6209,11 @@ case DID_AMD_17H_STARSHIP_DF_UMC: case DID_AMD_17H_RENOIR_DF_UMC: case DID_AMD_17H_ARIEL_DF_UMC: + case DID_AMD_17H_RAVEN2_DF_UMC: case DID_AMD_17H_FIREFLIGHT_DF_UMC: case DID_AMD_17H_ARDEN_DF_UMC: + case DID_AMD_19H_VERMEER_DF_UMC: + case DID_AMD_19H_CEZANNE_DF_UMC: AMD_17h_UMC(RO(Shm), RO(Proc)); AMD_17h_CAP(RO(Shm), RO(Proc), RO(Core)); SET_CHIPSET(IC_ZEN); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/corefreqk.c new/CoreFreq-1.91.6/corefreqk.c --- old/CoreFreq-1.91.3/corefreqk.c 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/corefreqk.c 2022-08-12 12:41:43.000000000 +0200 @@ -4687,7 +4687,7 @@ void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc) { /*Source: 12th Generation Intel?? Core Processor Datasheet Vol 2 */ - unsigned short cha; + unsigned short cha, channelCount; /* Intra channel configuration */ PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value = readl(mchmap+0xd800); @@ -4702,16 +4702,15 @@ /* DIMM parameters */ PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.value = readl(mchmap+0xd80c); PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.value = readl(mchmap+0xd810); - /* Sum up any present DIMM per channel. */ - PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = \ + /* Guessing activated channel from the populated DIMM. */ + channelCount = \ ((PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.Dimm_L_Size != 0) || (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.Dimm_S_Size != 0)) + ((PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.Dimm_L_Size != 0) || (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.Dimm_S_Size != 0)); - PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 2; - - for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++) + for (cha = 0 ; (cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount) + && (cha < channelCount); cha++) { PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].ADL.Timing.value = \ readq(mchmap + 0xe000 + 0x800 * cha); @@ -5540,13 +5539,32 @@ PCI_CALLBACK rc = 0; unsigned short mc; - PUBLIC(RO(Proc))->Uncore.CtrlCount = 2; + pci_read_config_dword(dev, 0xe4, + &PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_A.value); + + pci_read_config_dword(dev, 0xe8, + &PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_B.value); + + pci_read_config_dword(dev, 0xec, + &PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_C.value); + + pci_read_config_dword(dev, 0xf0, + &PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_E.value); + /* MCHBAR corresponds to bits 41 to 17 ; two MC x 64KB memory space */ - for (mc = 0; mc < PUBLIC(RO(Proc))->Uncore.CtrlCount; mc++) { + PUBLIC(RO(Proc))->Uncore.CtrlCount = 2; + for (mc = 0; mc < PUBLIC(RO(Proc))->Uncore.CtrlCount; mc++) + { + /* 2 DIMMs Per Channel Enable */ + if (PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_A.DDPCD == 0) { + PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 2; + } else { + PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 1; + } + PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 2; + rc = SKL_HOST(dev, Query_ADL_IMC, 0x10000, mc); } - pci_read_config_dword(dev, 0xf0, - &PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_E.value); return rc; } @@ -5663,7 +5681,8 @@ } static void AMD_Zen_UMC(struct pci_dev *dev, unsigned int UMC_BAR, - unsigned short mc, unsigned short cha) + unsigned short mc, unsigned short cha, + unsigned short cnt) { unsigned int CHIP_BAR[2][2] = { [0] = { @@ -5683,11 +5702,11 @@ Core_AMD_SMN_Read( PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].DIMM[slot].AMD17h.DAC, - SMU_AMD_UMC_BASE_CHA_F17H(cha) + 0x30 + (slot << 2), dev ); + SMU_AMD_UMC_BASE_CHA_F17H(cnt) + 0x30 + (slot << 2), dev ); Core_AMD_SMN_Read( PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].DIMM[slot].AMD17h.CFG, - SMU_AMD_UMC_BASE_CHA_F17H(cha) + 0x80 + (slot << 2), dev ); + SMU_AMD_UMC_BASE_CHA_F17H(cnt) + 0x80 + (slot << 2), dev ); for (sec = 0; sec < 2; sec++) { @@ -5774,7 +5793,8 @@ } static PCI_CALLBACK AMD_17h_DataFabric( struct pci_dev *pdev, - const unsigned short umc_max ) + const unsigned short umc_max, + const unsigned short dev_fun[] ) { struct pci_dev *dev; enum UNCORE_BOOST Mem_Clock = 0, Div_Clock = 0; @@ -5785,47 +5805,46 @@ for (umc = 0; umc < umc_max; umc++) { const unsigned int domain = pci_domain_nr(pdev->bus); - const unsigned int devfn = PCI_DEVFN(0x18 + umc, 0x0); - unsigned short cha; + const unsigned int devfn = PCI_DEVFN(dev_fun[umc], 0x0); + unsigned short cha = 0, cnt; dev = pci_get_domain_bus_and_slot(domain, 0x0, devfn); if (dev != NULL) { PUBLIC(RO(Proc))->Uncore.CtrlCount++; - PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount = 2; PUBLIC(RO(Proc))->Uncore.MC[umc].SlotCount = 2; - for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount; cha++) + for (cnt = 0; cnt < MC_MAX_CHA; cnt++) { AMD_17_UMC_SDP_CTRL SDP_CTRL = {.value = 0}; Core_AMD_SMN_Read( - PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cha].AMD17h.ECC._, - SMU_AMD_UMC_BASE_CHA_F17H(cha) + 0xdf0, dev ); + PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cnt].AMD17h.ECC._, + SMU_AMD_UMC_BASE_CHA_F17H(cnt) + 0xdf0, dev ); Core_AMD_SMN_Read( - PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cha].AMD17h.ECC.__, - SMU_AMD_UMC_BASE_CHA_F17H(cha) + 0xdf4, dev ); + PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cnt].AMD17h.ECC.__, + SMU_AMD_UMC_BASE_CHA_F17H(cnt) + 0xdf4, dev ); - Core_AMD_SMN_Read(SDP_CTRL, SMU_AMD_UMC_BASE_CHA_F17H(cha)+0x104, dev); + Core_AMD_SMN_Read(SDP_CTRL, SMU_AMD_UMC_BASE_CHA_F17H(cnt)+0x104, dev); if ((SDP_CTRL.value != 0xffffffff) && (SDP_CTRL.SdpInit)) { - AMD_Zen_UMC(dev, SMU_AMD_UMC_BASE_CHA_F17H(cha), umc, cha); + AMD_Zen_UMC(dev, SMU_AMD_UMC_BASE_CHA_F17H(cnt), umc, cha, cnt); + + cha++; } if ((Got_Mem_Clock == false) - && PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cha].AMD17h.MISC.MEMCLK) + && PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cnt].AMD17h.MISC.MEMCLK) { - Mem_Clock = PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[ - cha - ].AMD17h.MISC.MEMCLK; + Mem_Clock=PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cnt].AMD17h.MISC.MEMCLK; Got_Mem_Clock = true; } if (Got_Div_Clock == false) { AMD_17_UMC_DEBUG_MISC DbgMisc = {.value = 0}; - Core_AMD_SMN_Read(DbgMisc, SMU_AMD_UMC_BASE_CHA_F17H(cha) + 0xd6c, dev); + Core_AMD_SMN_Read(DbgMisc, SMU_AMD_UMC_BASE_CHA_F17H(cnt) + 0xd6c, dev); if (DbgMisc.UMC_Ready == 1) { Div_Clock = !DbgMisc.UCLK_Divisor; @@ -5833,6 +5852,7 @@ } } } + PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount = cha; pci_dev_put(dev); } else { pr_err( "CoreFreq: AMD_17h_DataFabric()" \ @@ -5854,61 +5874,57 @@ static PCI_CALLBACK AMD_DataFabric_Zeppelin(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Raven(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Matisse(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Starship(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Renoir(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Ariel(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Raven2(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Fireflight(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Arden(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Vermeer(struct pci_dev *pdev) { - return AMD_17h_DataFabric(pdev, 1); + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static PCI_CALLBACK AMD_DataFabric_Cezanne(struct pci_dev *pdev) { - if (PUBLIC(RO(Proc))->Registration.Experimental) { - return AMD_17h_DataFabric(pdev, 1); - } else { - return (PCI_CALLBACK) -EAGAIN; - } + return AMD_17h_DataFabric(pdev, 1, (const unsigned short[]){0x18}); } static void CoreFreqK_ResetChip(struct pci_dev *dev) @@ -20944,6 +20960,8 @@ return pStr; } +#define safe_strim(pStr) (strim(pStr == NULL ? "" : pStr)) + void SMBIOS_Entries(const struct dmi_header *dh, void *priv) { size_t *count = (size_t*) priv; @@ -20962,19 +20980,18 @@ case DMI_ENTRY_MEM_DEVICE: { const struct SMBIOS17 *entry = (struct SMBIOS17*) dh; - if ((entry->length >= 0x5c) && (entry->size > 0)) + if ((entry->length > 0x1a) && (entry->size > 0)) { if ((*count) < MC_MAX_DIMM) { const char *locator[2] = { - strim(SMBIOS_String(dh, entry->device_locator_id)), - strim(SMBIOS_String(dh, entry->bank_locator_id)) + safe_strim(SMBIOS_String(dh, entry->device_locator_id)), + safe_strim(SMBIOS_String(dh, entry->bank_locator_id)) }; - size_t calc; const size_t len[2] = { - (calc = strlen(locator[0])) > 0 ? calc : 0, - (calc = strlen(locator[1])) > 0 ? calc : 0 - }, prop = (calc = len[0] + len[1]) > 0 ? calc : 1; + strlen(locator[0]) > 0 ? strlen(locator[0]) : 0, + strlen(locator[1]) > 0 ? strlen(locator[1]) : 0 + }, prop = (len[0] + len[1]) > 0 ? (len[0] + len[1]) : 1; const int ratio[2] = { DIV_ROUND_CLOSEST(len[0] * (MAX_UTS_LEN - (1+1)), prop), @@ -20986,11 +21003,11 @@ ratio[1], locator[1]); StrCopy(PUBLIC(RO(Proc))->SMB.Memory.Manufacturer[(*count)], - strim(SMBIOS_String(dh, entry->manufacturer_id)), + safe_strim(SMBIOS_String(dh, entry->manufacturer_id)), MAX_UTS_LEN); StrCopy(PUBLIC(RO(Proc))->SMB.Memory.PartNumber[(*count)], - strim(SMBIOS_String(dh, entry->part_number_id)), + safe_strim(SMBIOS_String(dh, entry->part_number_id)), MAX_UTS_LEN); } } @@ -20999,6 +21016,7 @@ break; } } +#undef safe_strim #endif /* CONFIG_DMI */ void SMBIOS_Decoder(void) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/corefreqk.h new/CoreFreq-1.91.6/corefreqk.h --- old/CoreFreq-1.91.3/corefreqk.h 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/corefreqk.h 2022-08-12 12:41:43.000000000 +0200 @@ -2807,10 +2807,6 @@ PCI_VDEVICE(AMD, DID_AMD_17H_ARDEN_NB_IOMMU), .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU }, - { - PCI_VDEVICE(AMD, DID_AMD_19H_CEZANNE_NB_IOMMU), - .driver_data = (kernel_ulong_t) AMD_Zen_IOMMU - }, /* Source: HYGON: PCI list */ { PCI_VDEVICE(HYGON, DID_AMD_17H_ZEN_PLUS_NB_IOMMU), diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.91.3/coretypes.h new/CoreFreq-1.91.6/coretypes.h --- old/CoreFreq-1.91.3/coretypes.h 2022-06-19 22:04:16.000000000 +0200 +++ new/CoreFreq-1.91.6/coretypes.h 2022-08-12 12:41:43.000000000 +0200 @@ -6,7 +6,7 @@ #define COREFREQ_MAJOR 1 #define COREFREQ_MINOR 91 -#define COREFREQ_REV 3 +#define COREFREQ_REV 6 #if !defined(CORE_COUNT) #define CORE_COUNT 256
