Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2022-10-14 15:42:11 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new.2275 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Fri Oct 14 15:42:11 2022 rev:15 rq:1010511 version:20221003 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2022-08-13 22:37:02.738702207 +0200 +++ /work/SRC/openSUSE:Factory/.cpuid.new.2275/cpuid.changes 2022-10-14 15:43:17.211993299 +0200 @@ -1,0 +2,21 @@ +Thu Oct 13 14:05:28 UTC 2022 - Valentin Lefebvre <[email protected]> + +- Update to release 20221003 + * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1) + * Added synth & uarch synth decoding for + * (0,6),(11,5) Intel Meteor Lake + * (0,6),(11,6) Intel Grand Ridge (Crestmont) + * (0,6),(11,14) Intel Granite Rapids + * Renamed 7/0/eax enh hardware feedback to just "Thread + Director". + * Added 7/1/eax instructions. + * Added 0x12/0/eax SGX ENCLU EDECCSA flag. + * Added 0x23 Architecture Performance Monitoring Extended leaf + decoding. + * Corrected AVX512IFMA description: integer FMA, not just FMA. +- Release 20220927 + * Added synth decoding for (10,15),(6,1) Raphael + * Fixed title for AMD 0x8000001a leaf: Performance Optimization + identifiers. + +------------------------------------------------------------------- Old: ---- cpuid-20220812.src.tar.gz New: ---- cpuid-20221003.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.yKT9CZ/_old 2022-10-14 15:43:17.715994140 +0200 +++ /var/tmp/diff_new_pack.yKT9CZ/_new 2022-10-14 15:43:17.723994153 +0200 @@ -17,7 +17,7 @@ Name: cpuid -Version: 20220812 +Version: 20221003 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later @@ -35,7 +35,7 @@ Cyrix CPUs, and is fairly complete. %prep -%setup -q +%autosetup %build # remove -Werror=format-security which is used on Mandriva, as it produces @@ -52,6 +52,6 @@ %doc ChangeLog %license LICENSE %_bindir/* -%_mandir/man1/*.1%{?ext_man} +%_mandir/man1/*.1* %changelog ++++++ cpuid-20220812.src.tar.gz -> cpuid-20221003.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20220812/ChangeLog new/cpuid-20221003/ChangeLog --- old/cpuid-20220812/ChangeLog 2022-08-12 15:57:32.000000000 +0200 +++ new/cpuid-20221003/ChangeLog 2022-10-03 15:38:23.000000000 +0200 @@ -1,3 +1,46 @@ +Mon Oct 3 2022 Todd Allen <[email protected]> + * Made new release. + +Mon Oct 3 2022 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for AMD Ryzen (Phoenix E0), based on + sample from bakerlab.org. + * cpuid.c: Added synth decoding for AMD Ryzen (Storm Peak A1), based on + sample from einstein11.aei.uni-hannover.de. + * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,5) Intel + Meteor Lake, based on MSR_CPUID_table*. + * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,6) Intel + Grand Ridge (Crestmont), based on MSR_CPUID_table*. + * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,14) Intel + Granite Rapids, based on MSR_CPUID_table*. + * cpuid.c: Confirmed several other existing synth & uarch decodings based + on MSR_CPUID_table*, and updated comments (no functional changes). + * cpuid.c: Renamed 7/0/eax enh hardware feedback to simply Thread + Director. Evidently, Intel just calls it that now too. + * cpuid.c: Added 7/1/eax RAO-INT instructions, CMPccXADD instructions, + ArchPerfmonExt is valid, WRMSRNS instructions, AMX-FP16, AVX-IFMA, + RDMSRLIST & WRMSRLIST. + * cpuid.c: Added 7/1/edx AVX-VNNI-INT8, AVX-NE-CONVERT, PREFETCHIT* + instructions. + * cpuid.c: Added 0x12/0/eax SGX ENCLU EDECCSA flag. + * cpuid.c: Added 0x23 Architecture Performance Monitoring Extended leaf + decoding. + * cpuid.c: Corrected AVX512IFMA description: integer FMA, not just FMA. + +Tue Sep 27 2022 Todd Allen <[email protected]> + * Made new release. + +Tue Sep 27 2022 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for (10,15),(6,1) Raphael, based on + instlatx64 samples. + +Wed Aug 17 2022 Todd Allen <[email protected]> + * cpuid.c: Fixed missing return statement in get_nr_cpu_ids()'s default + case, used by Cygwin. Thanks to Brian Inglis for reporting this. + +Tue Aug 16 2022 Umio-Yasuno <[email protected]> + * cpuid.c: Fixed title for AMD 0x8000001a leaf: Performance Optimization + Identifiers. + Fri Aug 12 2022 Todd Allen <[email protected]> * Made new release. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20220812/FAMILY.NOTES new/cpuid-20221003/FAMILY.NOTES --- old/cpuid-20220812/FAMILY.NOTES 2022-08-12 15:25:33.000000000 +0200 +++ new/cpuid-20221003/FAMILY.NOTES 2022-10-03 13:41:23.000000000 +0200 @@ -110,7 +110,8 @@ 2020 Tremont Elkhart Lake Skyhawk Lake/ Jasper Lake ------------------------------------------------------------------------------------------------------------- - Gracemont + 2021 Gracemont + ------------------------------------------------------------------------------------------------------------- ? Crestmont ? Skymont ? Darkmont @@ -177,11 +178,13 @@ Network: uArch Core Platform SoC - ----------------------------------------------------- + ------------------------------------------------------ Silvermont Rangeley ? Rangeley - ----------------------------------------------------- + ------------------------------------------------------ Tremont Snow Ridge ? Snow Ridge - ----------------------------------------------------- + ------------------------------------------------------ + Crestmont? Grand Ridge ? Grand Ridge + ------------------------------------------------------ * Canceled core ! Surprising use of wrong-market core diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20220812/Makefile new/cpuid-20221003/Makefile --- old/cpuid-20220812/Makefile 2022-08-12 15:38:01.000000000 +0200 +++ new/cpuid-20221003/Makefile 2022-10-03 13:37:40.000000000 +0200 @@ -8,7 +8,7 @@ INSTALL_STRIP=-s PACKAGE=cpuid -VERSION=20220812 +VERSION=20221003 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20220812/cpuid.c new/cpuid-20221003/cpuid.c --- old/cpuid-20220812/cpuid.c 2022-08-12 15:52:50.000000000 +0200 +++ new/cpuid-20221003/cpuid.c 2022-10-03 15:34:33.000000000 +0200 @@ -2172,11 +2172,14 @@ FM ( 0, 6, 10, 6, *u = "Kaby Lake", *f = "Skylake", *p = "14nm+++"); // no spec update; only instlatx64 example FM ( 0, 6, 10, 7, *u = "Cypress Cove", *f = "Sunny Cove", *p = "14nm+++"); // LX* FM ( 0, 6, 10, 8, *u = "Cypress Cove", *f = "Sunny Cove", *p = "14nm+++"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,10, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,10, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,11, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // DPTF* - FM ( 0, 6, 10,12, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,13, *u = "Granite Rapids", *f = "Golden Cove", *p = "Intel 4"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,15, *u = "Sierra Forest"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,12, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,13, *u = "Granite Rapids", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,14, *u = "Granite Rapids", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table* + FM ( 0, 6, 10,15, *u = "Sierra Forest"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 11, 5, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table* + FM ( 0, 6, 11, 6, *u = "Crestmont", *p = "Intel 7"); // MSR_CPUID_table* (although assumption that Grand Ridge is Crestmont) FM ( 0, 6, 11, 7, *u = "Raptor Cove", *f = "Golden Cove", *p = "Intel 7"); // LX*, DPTF* FM ( 0, 6, 11,10, *u = "Raptor Cove", *f = "Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot* FM ( 0, 6, 11,14, *u = "Golden Cove", *p = "Intel 7"); // Coreboot* @@ -2310,6 +2313,7 @@ FM (10,15, 5, 0, *u = "Zen 3", *p = "7nm"); // undocumented, but instlatx64 samples FM (10,15, 5, 1, *u = "Zen 3", *p = "7nm"); FM (10,15, 6, 0, *u = "Zen 4", *p = "5nm"); // undocumented, but sample via instlatx64 from @patrickschur_ + FM (10,15, 6, 1, *u = "Zen 4", *p = "5nm"); // undocumented, but instlatx64 sample FM (10,15, 7, 0, *u = "Zen 4", *p = "5nm"); // undocumented, but sample via instlatx64 from @patrickschur_ FM (10,15, 10, 0, *u = "Zen 4c", *p = "5nm"); // undocumented, but sample via instlatx64 from @ExecuFix; 4c from 2021-11-8 roadmap from Lisa Su DEFAULT ((void)NULL); @@ -3583,18 +3587,21 @@ FM ( 0, 6, 10, 8, "Intel (unknown type) (Rocket Lake)"); // MSR_CPUID_table* FMS ( 0, 6, 10,10, 0, "Intel (unknown type) (Meteor Lake-M A0)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA; Coreboot* provides steppings. FMS ( 0, 6, 10,10, 1, "Intel (unknown type) (Meteor Lake-M A0)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA; Coreboot* provides steppings. - FM ( 0, 6, 10,10, "Intel (unknown type) (Meteor Lake-M)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,10, "Intel (unknown type) (Meteor Lake-M)"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,11, "Intel (unknown type) (Meteor Lake-N)"); // DPTF* - FM ( 0, 6, 10,12, "Intel (unknown type) (Meteor Lake-S)"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,13, "Intel (unknown type) (Granite Rapids)"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA - FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake)"); // LX*; DPTF* (which also says Raptor Lake-S) + FM ( 0, 6, 10,12, "Intel (unknown type) (Meteor Lake-S)"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,13, "Intel (unknown type) (Granite Rapids)"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 10,14, "Intel (unknown type) (Granite Rapids)"); // MSR_CPUID_table* + FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA + FM ( 0, 6, 11, 5, "Intel (unknown type) (Meteor Lake)"); // MSR_CPUID_table* + FM ( 0, 6, 11, 6, "Intel Atom (Grand Ridge)"); // MSR_CPUID_table* + FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake)"); // MSR_CPUID_table*; LX*; DPTF* (which also says Raptor Lake-S) FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-P J0)"); // Coreboot* FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)"); // Coreboot* FM ( 0, 6, 11,10, "Intel (unknown type) (Raptor Lake-P)"); // LX*; DPTF*; Coreboot* FMS ( 0, 6, 11,14, 0, "Intel (unknown type) (Alder Lake-N A0)"); // Coreboot* FM ( 0, 6, 11,14, "Intel (unknown type) (Alder Lake-N)"); // Coreboot*, LX* - FM ( 0, 6, 11,15, "Intel (unknown type) (Alder Lake)"); // MSR_CPUID_table* (or maybe Gracemont "little" cores tied to Alder Lake?) + FM ( 0, 6, 11,15, "Intel (unknown type) (Alder Lake)"); // MSR_CPUID_table* (or maybe Gracemont "little" cores tied to Alder Lake?); LX* thinks it's Raptor Lake-S FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); @@ -4544,11 +4551,13 @@ FMS (10,15, 0, 1, 1, "AMD EPYC (3rd Gen) (Milan B1)"); FMS (10,15, 0, 1, 2, "AMD EPYC (3rd Gen) (Milan B2)"); FM (10,15, 0, 1, "AMD EPYC (3rd Gen) (Milan)"); - FMS (10,15, 0, 8, 0, "AMD Ryzen Threadripper 5000 (Chagall A0)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix - FM (10,15, 0, 8, "AMD Ryzen Threadripper 5000 (Chagall)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix + FMS (10,15, 0, 8, 0, "AMD Ryzen Threadripper 5000 (Chagall A0)"); // undocumented, but sample from CCRT + FMS (10,15, 0, 8, 2, "AMD Ryzen Threadripper 5000 (Chagall A2)"); // undocumented, but sample from CCRT + FM (10,15, 0, 8, "AMD Ryzen Threadripper 5000 (Chagall)"); // undocumented, but sample from CCRT FMS (10,15, 1, 0, 0, "AMD EPYC (Genoa A0)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix FM (10,15, 1, 0, "AMD EPYC (Genoa)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix FMS (10,15, 1, 8, 0, "AMD Ryzen (Storm Peak A0)"); // undocumented, but (engr?) sample from @patrickschur_ + FMS (10,15, 1, 8, 1, "AMD Ryzen (Storm Peak A1)"); // undocumented, but engr sample via instlatx64 from einstein11.aei.uni-hannover.de (12981157) FM (10,15, 1, 8, "AMD Ryzen (Storm Peak)"); // undocumented, but (engr?) sample from @patrickschur_ FMS (10,15, 2, 1, 0, "AMD Ryzen 5000 (Vermeer B0)"); // undocumented, but instlatx64 samples FMS (10,15, 2, 1, 1, "AMD Ryzen 5000 (Vermeer B1)"); // undocumented, but sample from @patrickschur_ @@ -4566,8 +4575,12 @@ FM (10,15, 5, 1, "AMD Ryzen 5000 (Cezanne/Barcelo)"); FMS (10,15, 6, 0, 0, "AMD Ryzen (Raphael A0)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ FM (10,15, 6, 0, "AMD Ryzen (Raphael)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ + FMS (10,15, 6, 1, 2, "AMD Ryzen (Raphael B2)"); // undocumented, but instlatx64 sample + FM (10,15, 6, 1, "AMD Ryzen (Raphael)"); // undocumented, but instlatx64 sample FMS (10,15, 7, 0, 0, "AMD Ryzen (Phoenix A0)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ FM (10,15, 7, 0, "AMD Ryzen (Phoenix)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ + FMS (10,15, 7, 4, 0, "AMD Ryzen (Phoenix E0)"); // undocumented, but engr sample via instlatx64 from bakerlab.org (6220795) + FM (10,15, 7, 4, "AMD Ryzen (Phoenix)"); // undocumented, but engr sample via instlatx64 from bakerlab.org (6220795) FMS (10,15, 10, 0, 0, "AMD Ryzen (Bergamo A0)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix FM (10,15, 10, 0, "AMD Ryzen (Bergamo)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix F (10,15, "AMD (unknown model)"); @@ -5934,7 +5947,7 @@ { "IA32_HWP_REQUEST MSR fast access mode" , 18, 18, bools }, { "HW_FEEDBACK MSRs supported" , 19, 19, bools }, { "ignoring idle logical processor HWP req" , 20, 20, bools }, - { "enh hardware feedback (Thread Director)" , 23, 23, bools }, + { "Thread Director" , 23, 23, bools }, }; print_names(value, names, LENGTH(names), @@ -6005,7 +6018,7 @@ { "RDSEED instruction" , 18, 18, bools }, { "ADX instructions" , 19, 19, bools }, { "SMAP: supervisor mode access prevention" , 20, 20, bools }, - { "AVX512IFMA: fused multiply add" , 21, 21, bools }, + { "AVX512IFMA: integer fused multiply add" , 21, 21, bools }, // NOTE: AMD Appendix E.3.6 claims bit 22 is RDPID support, but this // almost certainly is an error. Section 3 RDPID description says it // is 7/0/ecx, as does Table 3-1. And this is consistent with Intel @@ -6079,7 +6092,7 @@ { "SRBDS mitigation MSR available" , 9, 9, bools }, { "VERW MD_CLEAR microcode support" , 10, 10, bools }, { "RTM transaction always aborts" , 11, 11, bools }, - { "TSX_FORCE_ABORT" , 13, 13, bools }, // LX* + { "TSX_FORCE_ABORT" , 13, 13, bools }, { "SERIALIZE instruction" , 14, 14, bools }, { "hybrid part" , 15, 15, bools }, { "TSXLDTRK: TSX suspend load addr tracking", 16, 16, bools }, @@ -6105,13 +6118,20 @@ print_7_1_eax(unsigned int value) { static named_item names[] - = { { "AVX-VNNI: AVX VNNI neural network instrs", 4, 4, bools }, + = { { "RAO-INT atomic instructions" , 3, 3, bools }, + { "AVX-VNNI: AVX VNNI neural network instrs", 4, 4, bools }, { "AVX512_BF16: bfloat16 instructions" , 5, 5, bools }, + { "CMPccXADD instructions" , 7, 7, bools }, + { "ArchPerfmonExt is valid" , 8, 8, bools }, { "fast zero-length MOVSB" , 10, 10, bools }, { "fast short STOSB" , 11, 11, bools }, { "fast short CMPSB, SCASB" , 12, 12, bools }, + { "WRMSRNS instruction" , 19, 19, bools }, + { "AMX-FP16: FP16 tile operations" , 21, 21, bools }, { "HRESET: history reset support" , 22, 22, bools }, + { "AVX-IFMA: integer fused multiply add" , 23, 23, bools }, { "LAM: linear address masking" , 26, 26, bools }, + { "RDMSRLIST, WRMSRLIST instructions" , 27, 27, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); @@ -6128,6 +6148,18 @@ } static void +print_7_1_edx(unsigned int value) +{ + static named_item names[] + = { { "AVX-VNNI-INT8 instructions" , 4, 4, bools }, + { "AVX-NE-CONVERT instructions" , 5, 5, bools }, + { "PREFETCHIT0, PREFETCHIT1 instructions" , 14, 14, bools }, + }; + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void print_7_2_edx(unsigned int value) { // Described in Intel's "Branch History Injection and Intra-mode Branch Target @@ -6562,6 +6594,7 @@ { "SGX ENCLV E*VIRTCHILD, ESETCONTEXT" , 5, 5, bools }, { "SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC", 6, 6, bools }, { "SGX ENCLU EVERIFYREPORT2" , 7, 7, bools }, + { "SGX ENCLU EDECCSSA" , 11, 11, bools }, }; print_names(value, names, LENGTH(names), @@ -7080,6 +7113,28 @@ } static void +print_23_3_eax(unsigned int value) +{ + static named_item names[] + = { { "core cycles" , 0, 0, bools }, + { "instructions retired" , 1, 1, bools }, + { "reference cycles" , 2, 2, bools }, + { "last level cache references" , 3, 3, bools }, + { "last level cache misses" , 4, 4, bools }, + { "branch instructions retired" , 5, 5, bools }, + { "branch mispredicts retired" , 6, 6, bools }, + { "topdown slots" , 7, 7, bools }, + { "topdown backend bound" , 8, 8, bools }, + { "topdown bad speculation" , 9, 9, bools }, + { "topdown frontend bound" , 10, 10, bools }, + { "topdown retiring" , 11, 11, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 0); +} + +static void print_20000001_edx(unsigned int value) { // I found a vague reference to this leaf in Intel Xeon Phi Coprocessor @@ -8484,7 +8539,7 @@ { "256-bit SSE executed full-width" , 2, 2, bools }, }; - printf(" SVM Secure Virtual Machine (0x8000001a/eax):\n"); + printf(" Performance Optimization Identifiers (0x8000001a/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } @@ -9389,6 +9444,7 @@ } else if (try == 1) { print_7_1_eax(words[WORD_EAX]); print_7_1_ebx(words[WORD_EBX]); + print_7_1_edx(words[WORD_EDX]); } else if (try == 2) { print_7_2_edx(words[WORD_EDX]); } else { @@ -9636,6 +9692,23 @@ } else { printf("none\n"); } + } else if (reg == 0x23) { + if (try == 0) { + printf(" Architecture Performance Monitoring Extended (0x23):\n"); + } else if (try == 1) { + printf(" general counters bitmap = 0x%0llx\n", + (unsigned long long)words[WORD_EAX]); + printf(" fixed counters bitmap = 0x%0llx\n", + (unsigned long long)words[WORD_EBX]); + } else if (try == 2) { + // All reserved + } else if (try == 3) { + printf(" Architecture Performance Monitoring Extended Supported Events" + " (0x23/3):\n"); + print_23_3_eax(words[WORD_EAX]); + } else { + print_reg_raw(reg, try, words); + } } else if (reg == 0x20000000) { // max already set to words[WORD_EAX] } else if (reg == 0x20000001) { @@ -10044,6 +10117,7 @@ #else unsigned long result = sysconf(_SC_NPROCESSORS_CONF); if (result > CPU_SETSIZE) result = CPU_SETSIZE; + return result; #endif } @@ -10497,6 +10571,15 @@ unsigned int max_tries = words[WORD_EAX]; unsigned int try = 0; for (;;) { + print_reg(reg, words, raw, try, &stash); + try++; + if (try > max_tries) break; + real_get(cpuid_fd, reg, words, try, FALSE); + } + } else if (reg == 0x23) { + unsigned int max_tries = words[WORD_EAX]; + unsigned int try = 0; + for (;;) { print_reg(reg, words, raw, try, &stash); try++; if (try > max_tries) break; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20220812/cpuid.man new/cpuid-20221003/cpuid.man --- old/cpuid-20220812/cpuid.man 2022-08-12 15:56:51.000000000 +0200 +++ new/cpuid-20221003/cpuid.man 2022-10-03 15:37:49.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20220812 2022/08/12 07:56:29 todd $ +.\" $Id: cpuid.man,v 20221003 2022/10/03 07:37:43 todd $ .\" -.TH CPUID 1 "12 Aug 2022" "20220812" +.TH CPUID 1 "3 Oct 2022" "20221003" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20220812/cpuid.spec new/cpuid-20221003/cpuid.spec --- old/cpuid-20220812/cpuid.spec 2022-08-12 15:58:09.000000000 +0200 +++ new/cpuid-20221003/cpuid.spec 2022-10-03 15:38:34.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20220812 +%define version 20221003 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
