Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package iverilog for openSUSE:Factory checked in at 2024-02-13 22:44:22 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/iverilog (Old) and /work/SRC/openSUSE:Factory/.iverilog.new.1815 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "iverilog" Tue Feb 13 22:44:22 2024 rev:9 rq:1146378 version:12.0 Changes: -------- --- /work/SRC/openSUSE:Factory/iverilog/iverilog.changes 2020-10-02 17:36:17.698702541 +0200 +++ /work/SRC/openSUSE:Factory/.iverilog.new.1815/iverilog.changes 2024-02-13 22:44:56.393803413 +0100 @@ -1,0 +2,7 @@ +Wed Feb 7 19:45:54 UTC 2024 - Wojciech Kazubski <[email protected]> + +- Update to version 12.0 + * This is the first release in the Version 12 branch. +- Updated URL and source locations + +------------------------------------------------------------------- Old: ---- verilog-11.0.tar.gz New: ---- verilog-12.0.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ iverilog.spec ++++++ --- /var/tmp/diff_new_pack.4m49MM/_old 2024-02-13 22:44:57.053827164 +0100 +++ /var/tmp/diff_new_pack.4m49MM/_new 2024-02-13 22:44:57.053827164 +0100 @@ -1,7 +1,7 @@ # # spec file for package iverilog # -# Copyright (c) 2020 SUSE LLC +# Copyright (c) 2020-2024 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,14 +17,14 @@ Name: iverilog -Version: 11.0 +Version: 12.0 Release: 0 -%define major_ver 11 +%define major_ver 12 Summary: Simulation and synthesis tool for IEEE-1364 License: GPL-2.0-or-later Group: Productivity/Scientific/Electronics -URL: http://iverilog.icarus.com/ -Source: ftp://icarus.com/pub/eda/verilog/v%{major_ver}/verilog-%{version}.tar.gz +URL: https://steveicarus.github.io/iverilog/ +Source: https://altushost-swe.dl.sourceforge.net/project/iverilog/iverilog/%{version}/verilog-%{version}.tar.gz BuildRequires: bison BuildRequires: fdupes BuildRequires: flex @@ -64,12 +64,12 @@ %files %license COPYING -%doc README.txt BUGS.txt QUICK_START.txt ieee1364-notes.txt +%doc README.md BUGS.txt QUICK_START.txt ieee1364-notes.txt %doc swift.txt netlist.txt t-dll.txt vpi.txt tgt-fpga/fpga.txt %doc cadpli/cadpli.txt xilinx-hint.txt examples -%{_mandir}/man1/* %{_bindir}/* %{_libdir}/ivl/ +%{_mandir}/man1/* %files devel %{_includedir}/* ++++++ verilog-11.0.tar.gz -> verilog-12.0.tar.gz ++++++ ++++ 364997 lines of diff (skipped)
