Author: matt
Date: 2007-09-24 19:20:22 -0600 (Mon, 24 Sep 2007)
New Revision: 6527
Modified:
gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v
Log:
fixed async resets and inverted resets
Modified:
gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v
2007-09-24 23:53:54 UTC (rev 6526)
+++ gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v
2007-09-25 01:20:22 UTC (rev 6527)
@@ -198,8 +198,8 @@
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
- always @(posedge clk_i or negedge rst_i)
- if (~rst_i)
+ always @(posedge clk_i)
+ if (rst_i)
begin
pol <= #1 {is{1'b0}}; // clear polarity register
edgen <= #1 {is{1'b0}}; // clear edge enable register
@@ -215,8 +215,8 @@
// pending register is a special case
- always @(posedge clk_i or negedge rst_i)
- if (~rst_i)
+ always @(posedge clk_i)
+ if (rst_i)
pending <= #1 {is{1'b0}}; // clear all pending interrupts
else if ( wb_wr & (&adr_i) )
pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event;
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